* makes it easier to do backend-specific optimizations than doing so
* in the GLSL IR or in the native code.
*/
-extern "C" {
-
#include <sys/types.h>
#include "main/macros.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_wm.h"
-}
#include "brw_vec4.h"
#include "brw_fs.h"
#include "main/uniforms.h"
fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
const fs_reg &src0, const fs_reg &src1)
{
+ assert(conditionalmod == BRW_CONDITIONAL_GE ||
+ conditionalmod == BRW_CONDITIONAL_L);
+
fs_inst *inst;
if (brw->gen >= 6) {
if (ir->type != glsl_type::float_type)
return false;
- ir_rvalue *nonmul = ir->operands[1];
- ir_expression *mul = ir->operands[0]->as_expression();
+ ir_rvalue *nonmul;
+ ir_expression *mul;
+ bool mul_negate, mul_abs;
- bool mul_negate = false, mul_abs = false;
- if (mul && mul->operation == ir_unop_abs) {
- mul = mul->operands[0]->as_expression();
- mul_abs = true;
- } else if (mul && mul->operation == ir_unop_neg) {
- mul = mul->operands[0]->as_expression();
- mul_negate = true;
- }
+ for (int i = 0; i < 2; i++) {
+ mul_negate = false;
+ mul_abs = false;
- if (!mul || mul->operation != ir_binop_mul) {
- nonmul = ir->operands[0];
- mul = ir->operands[1]->as_expression();
+ mul = ir->operands[i]->as_expression();
+ nonmul = ir->operands[1 - i];
if (mul && mul->operation == ir_unop_abs) {
mul = mul->operands[0]->as_expression();
mul_negate = true;
}
- if (!mul || mul->operation != ir_binop_mul)
- return false;
+ if (mul && mul->operation == ir_binop_mul)
+ break;
}
+ if (!mul || mul->operation != ir_binop_mul)
+ return false;
+
nonmul->accept(this);
fs_reg src0 = this->result;
case ir_binop_interpolate_at_sample:
unreachable("already handled above");
break;
+
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
+ unreachable("fp64 todo");
+ break;
}
}
case GLSL_TYPE_ATOMIC_UINT:
break;
+ case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
chan = offset(chan, i);
inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
- inst->conditional_mod = BRW_CONDITIONAL_G;
+ inst->conditional_mod = BRW_CONDITIONAL_GE;
/* Our parameter comes in as 1.0/width or 1.0/height,
* because that's what people normally want for doing
fs_reg shadow_c,
fs_reg lod, fs_reg lod2, int grad_components,
fs_reg sample_index,
- fs_reg offset_value, unsigned offset_components,
+ fs_reg offset_value,
fs_reg mcs,
int gather_component,
bool is_cube_array,
}
fs_reg offset_value;
- int offset_components = 0;
if (ir->offset) {
ir_constant *const_offset = ir->offset->as_constant();
if (const_offset) {
ir->offset->accept(this);
offset_value = this->result;
}
- offset_components = ir->offset->type->vector_elements;
}
fs_reg lod, lod2, sample_index, mcs;
emit_texture(ir->op, ir->type, coordinate, coord_components,
shadow_comparitor, lod, lod2, grad_components,
- sample_index, offset_value, offset_components, mcs,
+ sample_index, offset_value, mcs,
gather_component, is_cube_array, is_rect, sampler,
sampler_reg, texunit);
}
void
fs_visitor::visit(ir_discard *ir)
{
- assert(ir->condition == NULL); /* FINISHME */
-
/* We track our discarded pixels in f0.1. By predicating on it, we can
- * update just the flag bits that aren't yet discarded. By emitting a
- * CMP of g0 != g0, all our currently executing channels will get turned
- * off.
+ * update just the flag bits that aren't yet discarded. If there's no
+ * condition, we emit a CMP of g0 != g0, so all currently executing
+ * channels will get turned off.
*/
- fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
- BRW_REGISTER_TYPE_UW));
- fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
- BRW_CONDITIONAL_NZ));
+ fs_inst *cmp;
+ if (ir->condition) {
+ emit_bool_to_cond_code(ir->condition);
+ cmp = (fs_inst *) this->instructions.get_tail();
+ cmp->conditional_mod = brw_negate_cmod(cmp->conditional_mod);
+ } else {
+ fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
+ BRW_REGISTER_TYPE_UW));
+ cmp = emit(CMP(reg_null_f, some_reg, some_reg, BRW_CONDITIONAL_NZ));
+ }
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
emit(IF(this->result, fs_reg(0), BRW_CONDITIONAL_NZ));
}
+bool
+fs_visitor::try_opt_frontfacing_ternary(ir_if *ir)
+{
+ ir_dereference_variable *deref = ir->condition->as_dereference_variable();
+ if (!deref || strcmp(deref->var->name, "gl_FrontFacing") != 0)
+ return false;
+
+ if (ir->then_instructions.length() != 1 ||
+ ir->else_instructions.length() != 1)
+ return false;
+
+ ir_assignment *then_assign =
+ ((ir_instruction *)ir->then_instructions.head)->as_assignment();
+ ir_assignment *else_assign =
+ ((ir_instruction *)ir->else_instructions.head)->as_assignment();
+
+ if (!then_assign || then_assign->condition ||
+ !else_assign || else_assign->condition ||
+ then_assign->write_mask != else_assign->write_mask ||
+ !then_assign->lhs->equals(else_assign->lhs))
+ return false;
+
+ ir_constant *then_rhs = then_assign->rhs->as_constant();
+ ir_constant *else_rhs = else_assign->rhs->as_constant();
+
+ if (!then_rhs || !else_rhs)
+ return false;
+
+ if ((then_rhs->is_one() || then_rhs->is_negative_one()) &&
+ (else_rhs->is_one() || else_rhs->is_negative_one())) {
+ assert(then_rhs->is_one() == else_rhs->is_negative_one());
+ assert(else_rhs->is_one() == then_rhs->is_negative_one());
+
+ then_assign->lhs->accept(this);
+ fs_reg dst = this->result;
+ dst.type = BRW_REGISTER_TYPE_D;
+ fs_reg tmp = vgrf(glsl_type::int_type);
+
+ if (brw->gen >= 6) {
+ /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
+ fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
+ */
+
+ if (then_rhs->is_negative_one()) {
+ assert(else_rhs->is_one());
+ g0.negate = true;
+ }
+
+ tmp.type = BRW_REGISTER_TYPE_W;
+ tmp.subreg_offset = 2;
+ tmp.stride = 2;
+
+ fs_inst *or_inst = emit(OR(tmp, g0, fs_reg(0x3f80)));
+ or_inst->src[1].type = BRW_REGISTER_TYPE_UW;
+
+ tmp.type = BRW_REGISTER_TYPE_D;
+ tmp.subreg_offset = 0;
+ tmp.stride = 1;
+ } else {
+ /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
+ fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
+ */
+
+ if (then_rhs->is_negative_one()) {
+ assert(else_rhs->is_one());
+ g1_6.negate = true;
+ }
+
+ emit(OR(tmp, g1_6, fs_reg(0x3f800000)));
+ }
+ emit(AND(dst, tmp, fs_reg(0xbf800000)));
+ return true;
+ }
+
+ return false;
+}
+
/**
* Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
*
void
fs_visitor::visit(ir_if *ir)
{
+ if (try_opt_frontfacing_ternary(ir))
+ return;
+
/* Don't point the annotation at the if statement, because then it plus
* the then and else blocks get printed.
*/
* mask sent in the header to compute the actual set of channels that execute
* the atomic operation.
*/
- assert(stage == MESA_SHADER_VERTEX);
+ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
emit(MOV(component(sources[0], 7),
- brw_imm_ud(0xff)))->force_writemask_all = true;
+ fs_reg(0xffff)))->force_writemask_all = true;
}
length++;
* mask sent in the header to compute the actual set of channels that execute
* the atomic operation.
*/
- assert(stage == MESA_SHADER_VERTEX);
+ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
emit(MOV(component(sources[0], 7),
- brw_imm_ud(0xff)))->force_writemask_all = true;
+ fs_reg(0xffff)))->force_writemask_all = true;
}
/* Set the surface read offset. */
}
int
-fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components)
+fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
+ bool use_2nd_half)
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
fs_inst *inst;
colors_enabled = (1 << components) - 1;
}
- if (dispatch_width == 8 || brw->gen >= 6) {
+ if (dispatch_width == 8 || (brw->gen >= 6 && !do_dual_src)) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1
len++;
}
return len;
+ } else if (brw->gen >= 6 && do_dual_src) {
+ /* SIMD16 dual source blending for gen6+.
+ *
+ * From the SNB PRM, volume 4, part 1, page 193:
+ *
+ * "The dual source render target messages only have SIMD8 forms due to
+ * maximum message length limitations. SIMD16 pixel shaders must send two
+ * of these messages to cover all of the pixels. Each message contains
+ * two colors (4 channels each) for each pixel in the message payload."
+ *
+ * So in SIMD16 dual source blending we will send 2 SIMD8 messages,
+ * each one will call this function twice (one for each color involved),
+ * so in each pass we only write 4 registers. Notice that the second
+ * SIMD8 message needs to read color data from the 2nd half of the color
+ * registers, so it needs to call this with use_2nd_half = true.
+ */
+ for (unsigned i = 0; i < 4; ++i) {
+ if (colors_enabled & (1 << i)) {
+ dst[i] = fs_reg(GRF, alloc.allocate(1), color.type);
+ inst = emit(MOV(dst[i], half(offset(color, i),
+ use_2nd_half ? 1 : 0)));
+ inst->saturate = key->clamp_fragment_color;
+ if (use_2nd_half)
+ inst->force_sechalf = true;
+ }
+ }
+ return 4;
} else {
/* pre-gen6 SIMD16 single source DP write looks like:
* m + 0: r0
fs_inst *
fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1,
- fs_reg src0_alpha, unsigned components)
+ fs_reg src0_alpha, unsigned components,
+ bool use_2nd_half)
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
* alpha out the pipeline to our null renderbuffer to support
* alpha-testing, alpha-to-coverage, and so on.
*/
- length += setup_color_payload(sources + length, this->outputs[0], 0);
+ length += setup_color_payload(sources + length, this->outputs[0], 0,
+ false);
} else if (color1.file == BAD_FILE) {
if (src0_alpha.file != BAD_FILE) {
sources[length] = fs_reg(GRF, alloc.allocate(reg_size),
length++;
}
- length += setup_color_payload(sources + length, color0, components);
+ length += setup_color_payload(sources + length, color0, components,
+ false);
} else {
- length += setup_color_payload(sources + length, color0, components);
- length += setup_color_payload(sources + length, color1, components);
+ length += setup_color_payload(sources + length, color0, components,
+ use_2nd_half);
+ length += setup_color_payload(sources + length, color1, components,
+ use_2nd_half);
}
if (source_depth_to_render_target) {
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- if (do_dual_src) {
- no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
- if (dispatch_width == 16)
- do_dual_src = false;
- }
-
fs_inst *inst;
if (do_dual_src) {
if (INTEL_DEBUG & DEBUG_SHADER_TIME)
inst = emit_single_fb_write(this->outputs[0], this->dual_src_output,
reg_undef, 4);
inst->target = 0;
+
+ /* SIMD16 dual source blending requires to send two SIMD8 dual source
+ * messages, where each message contains color data for 8 pixels. Color
+ * data for the first group of pixels is stored in the "lower" half of
+ * the color registers, so in SIMD16, the previous message did:
+ * m + 0: r0
+ * m + 1: g0
+ * m + 2: b0
+ * m + 3: a0
+ *
+ * Here goes the second message, which packs color data for the
+ * remaining 8 pixels. Color data for these pixels is stored in the
+ * "upper" half of the color registers, so we need to do:
+ * m + 0: r1
+ * m + 1: g1
+ * m + 2: b1
+ * m + 3: a1
+ */
+ if (dispatch_width == 16) {
+ inst = emit_single_fb_write(this->outputs[0], this->dual_src_output,
+ reg_undef, 4, true);
+ inst->target = 0;
+ }
+
prog_data->dual_src_blend = true;
} else if (key->nr_color_regions > 0) {
for (int target = 0; target < key->nr_color_regions; target++) {
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