* makes it easier to do backend-specific optimizations than doing so
* in the GLSL IR or in the native code.
*/
-extern "C" {
-
#include <sys/types.h>
#include "main/macros.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_wm.h"
-}
#include "brw_vec4.h"
#include "brw_fs.h"
#include "main/uniforms.h"
fs_reg *
-fs_visitor::emit_vs_system_value(enum brw_reg_type type, int location)
+fs_visitor::emit_vs_system_value(int location)
{
fs_reg *reg = new(this->mem_ctx)
- fs_reg(ATTR, VERT_ATTRIB_MAX, type);
+ fs_reg(ATTR, VERT_ATTRIB_MAX, BRW_REGISTER_TYPE_D);
brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data;
switch (location) {
reg = new(this->mem_ctx)
fs_reg(ATTR, ir->data.location,
brw_type_for_base_type(ir->type->get_scalar_type()));
- } else if (!strcmp(ir->name, "gl_FragCoord")) {
+ } else if (ir->data.location == VARYING_SLOT_POS) {
reg = emit_fragcoord_interpolation(ir->data.pixel_center_integer,
ir->data.origin_upper_left);
- } else if (!strcmp(ir->name, "gl_FrontFacing")) {
+ } else if (ir->data.location == VARYING_SLOT_FACE) {
reg = emit_frontfacing_interpolation();
} else {
- reg = new(this->mem_ctx) fs_reg(this, ir->type);
+ reg = new(this->mem_ctx) fs_reg(vgrf(ir->type));
emit_general_interpolation(*reg, ir->name, ir->type,
(glsl_interp_qualifier) ir->data.interpolation,
ir->data.location, ir->data.centroid,
hash_table_insert(this->variable_ht, reg, ir);
return;
} else if (ir->data.mode == ir_var_shader_out) {
- reg = new(this->mem_ctx) fs_reg(this, ir->type);
+ reg = new(this->mem_ctx) fs_reg(vgrf(ir->type));
if (stage == MESA_SHADER_VERTEX) {
int vector_elements =
case SYSTEM_VALUE_VERTEX_ID:
case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
case SYSTEM_VALUE_INSTANCE_ID:
- reg = emit_vs_system_value(brw_type_for_base_type(ir->type),
- ir->data.location);
+ reg = emit_vs_system_value(ir->data.location);
break;
case SYSTEM_VALUE_SAMPLE_POS:
reg = emit_samplepos_setup();
}
if (!reg)
- reg = new(this->mem_ctx) fs_reg(this, ir->type);
+ reg = new(this->mem_ctx) fs_reg(vgrf(ir->type));
hash_table_insert(this->variable_ht, reg, ir);
}
ir->array_index->accept(this);
fs_reg index_reg;
- index_reg = fs_reg(this, glsl_type::int_type);
+ index_reg = vgrf(glsl_type::int_type);
emit(BRW_OPCODE_MUL, index_reg, this->result, fs_reg(element_size));
if (src.reladdr) {
{
if (brw->gen < 6) {
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
- fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
- fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
- fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
+ fs_reg y_times_a = vgrf(glsl_type::float_type);
+ fs_reg one_minus_a = vgrf(glsl_type::float_type);
+ fs_reg x_times_one_minus_a = vgrf(glsl_type::float_type);
emit(MUL(y_times_a, y, a));
fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
const fs_reg &src0, const fs_reg &src1)
{
+ assert(conditionalmod == BRW_CONDITIONAL_GE ||
+ conditionalmod == BRW_CONDITIONAL_L);
+
fs_inst *inst;
if (brw->gen >= 6) {
non_const_mul->accept(this);
fs_reg src1 = this->result;
- fs_reg src0 = fs_reg(this, ir->type);
+ fs_reg src0 = vgrf(ir->type);
emit(BRW_OPCODE_MOV, src0,
fs_reg((uint8_t)mul_operand_vf, 0, 0, (uint8_t)add_operand_vf));
- this->result = fs_reg(this, ir->type);
+ this->result = vgrf(ir->type);
emit(BRW_OPCODE_LINE, this->result, src0, src1);
return true;
}
if (ir->type != glsl_type::float_type)
return false;
- ir_rvalue *nonmul = ir->operands[1];
- ir_expression *mul = ir->operands[0]->as_expression();
+ ir_rvalue *nonmul;
+ ir_expression *mul;
+ bool mul_negate, mul_abs;
- bool mul_negate = false, mul_abs = false;
- if (mul && mul->operation == ir_unop_abs) {
- mul = mul->operands[0]->as_expression();
- mul_abs = true;
- } else if (mul && mul->operation == ir_unop_neg) {
- mul = mul->operands[0]->as_expression();
- mul_negate = true;
- }
+ for (int i = 0; i < 2; i++) {
+ mul_negate = false;
+ mul_abs = false;
- if (!mul || mul->operation != ir_binop_mul) {
- nonmul = ir->operands[0];
- mul = ir->operands[1]->as_expression();
+ mul = ir->operands[i]->as_expression();
+ nonmul = ir->operands[1 - i];
if (mul && mul->operation == ir_unop_abs) {
mul = mul->operands[0]->as_expression();
mul_negate = true;
}
- if (!mul || mul->operation != ir_binop_mul)
- return false;
+ if (mul && mul->operation == ir_binop_mul)
+ break;
}
- if (nonmul->as_constant() ||
- mul->operands[0]->as_constant() ||
- mul->operands[1]->as_constant())
+ if (!mul || mul->operation != ir_binop_mul)
return false;
nonmul->accept(this);
if (mul_abs)
src2.negate = false;
- this->result = fs_reg(this, ir->type);
+ this->result = vgrf(ir->type);
emit(BRW_OPCODE_MAD, this->result, src0, src1, src2);
return true;
/* 1. collect interpolation factors */
- fs_reg dst_x = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 2, 1));
+ fs_reg dst_x = vgrf(glsl_type::get_instance(ir->type->base_type, 2, 1));
fs_reg dst_y = offset(dst_x, 1);
/* for most messages, we need one reg of ignored data; the hardware requires mlen==1
* even when there is no payload. in the per-slot offset case, we'll replace this with
* the proper source data. */
- fs_reg src = fs_reg(this, glsl_type::float_type);
+ fs_reg src = vgrf(glsl_type::float_type);
int mlen = 1; /* one reg unless overriden */
int reg_width = dispatch_width / 8;
fs_inst *inst;
} else {
/* pack the operands: hw wants offsets as 4 bit signed ints */
ir->operands[1]->accept(this);
- src = fs_reg(this, glsl_type::ivec2_type);
+ src = vgrf(glsl_type::ivec2_type);
fs_reg src2 = src;
for (int i = 0; i < 2; i++) {
- fs_reg temp = fs_reg(this, glsl_type::float_type);
+ fs_reg temp = vgrf(glsl_type::float_type);
emit(MUL(temp, this->result, fs_reg(16.0f)));
emit(MOV(src2, temp)); /* float to int */
/* 2. emit linterp */
- fs_reg res(this, ir->type);
+ fs_reg res = vgrf(ir->type);
this->result = res;
for (int i = 0; i < ir->type->vector_elements; i++) {
emit_bool_to_cond_code(ir->operands[0]);
- this->result = fs_reg(this, ir->type);
+ this->result = vgrf(ir->type);
inst = emit(SEL(this->result, op[1], op[2]));
inst->predicate = BRW_PREDICATE_NORMAL;
return;
/* Storage for our result. If our result goes into an assignment, it will
* just get copy-propagated out, so no worries.
*/
- this->result = fs_reg(this, ir->type);
+ this->result = vgrf(ir->type);
switch (ir->operation) {
case ir_unop_logic_not:
break;
}
case ir_binop_mod:
- /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
+ /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
assert(ir->type->is_integer());
emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]);
break;
emit(RNDZ(this->result, op[0]));
break;
case ir_unop_ceil: {
- fs_reg tmp = fs_reg(this, ir->type);
+ fs_reg tmp = vgrf(ir->type);
op[0].negate = !op[0].negate;
emit(RNDD(tmp, op[0]));
tmp.negate = true;
emit(CBIT(this->result, op[0]));
break;
case ir_unop_find_msb:
- temp = fs_reg(this, glsl_type::uint_type);
+ temp = vgrf(glsl_type::uint_type);
emit(FBH(temp, op[0]));
/* FBH counts from the MSB side, while GLSL's findMSB() wants the count
* per-channel and add the base UBO index; the generator will select
* a value from any live channel.
*/
- surf_index = fs_reg(this, glsl_type::uint_type);
+ surf_index = vgrf(glsl_type::uint_type);
emit(ADD(surf_index, op[0],
fs_reg(stage_prog_data->binding_table.ubo_start)))
->force_writemask_all = true;
}
if (const_offset) {
- fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
+ fs_reg packed_consts = vgrf(glsl_type::float_type);
packed_consts.type = result.type;
fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
}
} else {
/* Turn the byte offset into a dword offset. */
- fs_reg base_offset = fs_reg(this, glsl_type::int_type);
+ fs_reg base_offset = vgrf(glsl_type::int_type);
emit(SHR(base_offset, op[1], fs_reg(2)));
for (int i = 0; i < ir->type->vector_elements; i++) {
case ir_binop_interpolate_at_sample:
unreachable("already handled above");
break;
+
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
+ unreachable("fp64 todo");
+ break;
}
}
case GLSL_TYPE_ATOMIC_UINT:
break;
+ case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
/* If last_rhs_inst wrote a different number of components than our LHS,
* we can't safely rewrite it.
*/
- if (virtual_grf_sizes[dst.reg] != modify->regs_written)
+ if (alloc.sizes[dst.reg] != modify->regs_written)
return false;
/* Success! Rewrite the instruction. */
* this weirdness around to the expected layout.
*/
orig_dst = dst;
- dst = fs_reg(GRF, virtual_grf_alloc(8), orig_dst.type);
+ dst = fs_reg(GRF, alloc.allocate(8), orig_dst.type);
}
enum opcode opcode;
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, MAX_SAMPLER_MESSAGE_SIZE);
for (int i = 0; i < MAX_SAMPLER_MESSAGE_SIZE; i++) {
- sources[i] = fs_reg(this, glsl_type::float_type);
+ sources[i] = vgrf(glsl_type::float_type);
}
int length = 0;
* need to offset the Sampler State Pointer in the header.
*/
header_present = true;
- sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
+ sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
length++;
}
else
mlen = length * reg_width;
- fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
+ fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
BRW_REGISTER_TYPE_F);
emit(LOAD_PAYLOAD(src_payload, sources, length));
* tracking to get the scaling factor.
*/
if (brw->gen < 6 && is_rect) {
- fs_reg dst = fs_reg(GRF, virtual_grf_alloc(coord_components));
+ fs_reg dst = fs_reg(GRF, alloc.allocate(coord_components));
fs_reg src = coordinate;
coordinate = dst;
chan = offset(chan, i);
inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
- inst->conditional_mod = BRW_CONDITIONAL_G;
+ inst->conditional_mod = BRW_CONDITIONAL_GE;
/* Our parameter comes in as 1.0/width or 1.0/height,
* because that's what people normally want for doing
* for clamping, but we don't care enough to make a new
* parameter type, so just invert back.
*/
- fs_reg limit = fs_reg(this, glsl_type::float_type);
+ fs_reg limit = vgrf(glsl_type::float_type);
emit(MOV(limit, i == 0 ? scale_x : scale_y));
emit(SHADER_OPCODE_RCP, limit, limit);
fs_visitor::emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler)
{
int reg_width = dispatch_width / 8;
- fs_reg payload = fs_reg(GRF, virtual_grf_alloc(components * reg_width),
+ fs_reg payload = fs_reg(GRF, alloc.allocate(components * reg_width),
BRW_REGISTER_TYPE_F);
- fs_reg dest = fs_reg(this, glsl_type::uvec4_type);
+ fs_reg dest = vgrf(glsl_type::uvec4_type);
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, components);
/* parameters are: u, v, r; missing parameters are treated as zero */
for (int i = 0; i < components; i++) {
- sources[i] = fs_reg(this, glsl_type::float_type);
+ sources[i] = vgrf(glsl_type::float_type);
emit(MOV(retype(sources[i], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
}
fs_reg shadow_c,
fs_reg lod, fs_reg lod2, int grad_components,
fs_reg sample_index,
- fs_reg offset_value, unsigned offset_components,
+ fs_reg offset_value,
fs_reg mcs,
int gather_component,
bool is_cube_array,
int swiz = GET_SWZ(tex->swizzles[sampler], gather_component);
if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
- fs_reg res = fs_reg(this, glsl_type::vec4_type);
+ fs_reg res = vgrf(glsl_type::vec4_type);
this->result = res;
for (int i=0; i<4; i++) {
/* Writemasking doesn't eliminate channels on SIMD8 texture
* samples, so don't worry about them.
*/
- fs_reg dst(this, glsl_type::get_instance(dest_type->base_type, 4, 1));
+ fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 4, 1));
if (brw->gen >= 7) {
inst = emit_texture_gen7(op, dst, coordinate, coord_components,
/* fixup #layers for cube map arrays */
if (op == ir_txs && is_cube_array) {
fs_reg depth = offset(dst, 2);
- fs_reg fixed_depth = fs_reg(this, glsl_type::int_type);
+ fs_reg fixed_depth = vgrf(glsl_type::int_type);
emit_math(SHADER_OPCODE_INT_QUOTIENT, fixed_depth, depth, fs_reg(6));
fs_reg *fixed_payload = ralloc_array(mem_ctx, fs_reg, inst->regs_written);
/* Emit code to evaluate the actual indexing expression */
nonconst_sampler_index->accept(this);
- fs_reg temp(this, glsl_type::uint_type);
+ fs_reg temp = vgrf(glsl_type::uint_type);
emit(ADD(temp, this->result, fs_reg(sampler)))
->force_writemask_all = true;
sampler_reg = temp;
}
fs_reg offset_value;
- int offset_components = 0;
if (ir->offset) {
ir_constant *const_offset = ir->offset->as_constant();
if (const_offset) {
ir->offset->accept(this);
offset_value = this->result;
}
- offset_components = ir->offset->type->vector_elements;
}
fs_reg lod, lod2, sample_index, mcs;
emit_texture(ir->op, ir->type, coordinate, coord_components,
shadow_comparitor, lod, lod2, grad_components,
- sample_index, offset_value, offset_components, mcs,
+ sample_index, offset_value, mcs,
gather_component, is_cube_array, is_rect, sampler,
sampler_reg, texunit);
}
if (dest_components == 1) {
/* Ignore DEPTH_TEXTURE_MODE swizzling. */
} else if (tex->swizzles[sampler] != SWIZZLE_NOOP) {
- fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
+ fs_reg swizzled_result = vgrf(glsl_type::vec4_type);
swizzled_result.type = orig_val.type;
for (int i = 0; i < 4; i++) {
return;
}
- fs_reg result = fs_reg(this, ir->type);
+ fs_reg result = vgrf(ir->type);
this->result = result;
for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
void
fs_visitor::visit(ir_discard *ir)
{
- assert(ir->condition == NULL); /* FINISHME */
-
/* We track our discarded pixels in f0.1. By predicating on it, we can
- * update just the flag bits that aren't yet discarded. By emitting a
- * CMP of g0 != g0, all our currently executing channels will get turned
- * off.
+ * update just the flag bits that aren't yet discarded. If there's no
+ * condition, we emit a CMP of g0 != g0, so all currently executing
+ * channels will get turned off.
*/
- fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
- BRW_REGISTER_TYPE_UW));
- fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
- BRW_CONDITIONAL_NZ));
+ fs_inst *cmp;
+ if (ir->condition) {
+ emit_bool_to_cond_code(ir->condition);
+ cmp = (fs_inst *) this->instructions.get_tail();
+ cmp->conditional_mod = brw_negate_cmod(cmp->conditional_mod);
+ } else {
+ fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
+ BRW_REGISTER_TYPE_UW));
+ cmp = emit(CMP(reg_null_f, some_reg, some_reg, BRW_CONDITIONAL_NZ));
+ }
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
* Make reg constant so that it doesn't get accidentally modified along the
* way. Yes, I actually had this problem. :(
*/
- const fs_reg reg(this, ir->type);
+ const fs_reg reg = vgrf(ir->type);
fs_reg dst_reg = reg;
if (ir->type->is_array()) {
case ir_binop_logic_xor:
if (brw->gen <= 5) {
- fs_reg temp = fs_reg(this, ir->type);
+ fs_reg temp = vgrf(ir->type);
emit(XOR(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
} else {
case ir_binop_logic_or:
if (brw->gen <= 5) {
- fs_reg temp = fs_reg(this, ir->type);
+ fs_reg temp = vgrf(ir->type);
emit(OR(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
} else {
case ir_binop_logic_and:
if (brw->gen <= 5) {
- fs_reg temp = fs_reg(this, ir->type);
+ fs_reg temp = vgrf(ir->type);
emit(AND(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
} else {
inst->conditional_mod = BRW_CONDITIONAL_NZ;
/* Select which boolean to return. */
- fs_reg temp(this, expr->operands[1]->type);
+ fs_reg temp = vgrf(expr->operands[1]->type);
inst = emit(SEL(temp, op[1], op[2]));
inst->predicate = BRW_PREDICATE_NORMAL;
return;
case ir_binop_logic_or:
- temp = fs_reg(this, glsl_type::bool_type);
+ temp = vgrf(glsl_type::bool_type);
emit(OR(temp, op[0], op[1]));
emit(IF(temp, fs_reg(0), BRW_CONDITIONAL_NZ));
return;
case ir_binop_logic_and:
- temp = fs_reg(this, glsl_type::bool_type);
+ temp = vgrf(glsl_type::bool_type);
emit(AND(temp, op[0], op[1]));
emit(IF(temp, fs_reg(0), BRW_CONDITIONAL_NZ));
return;
inst->conditional_mod = BRW_CONDITIONAL_NZ;
/* Select which boolean to use as the result. */
- fs_reg temp(this, expr->operands[1]->type);
+ fs_reg temp = vgrf(expr->operands[1]->type);
inst = emit(SEL(temp, op[1], op[2]));
inst->predicate = BRW_PREDICATE_NORMAL;
emit(IF(this->result, fs_reg(0), BRW_CONDITIONAL_NZ));
}
+bool
+fs_visitor::try_opt_frontfacing_ternary(ir_if *ir)
+{
+ ir_dereference_variable *deref = ir->condition->as_dereference_variable();
+ if (!deref || strcmp(deref->var->name, "gl_FrontFacing") != 0)
+ return false;
+
+ if (ir->then_instructions.length() != 1 ||
+ ir->else_instructions.length() != 1)
+ return false;
+
+ ir_assignment *then_assign =
+ ((ir_instruction *)ir->then_instructions.head)->as_assignment();
+ ir_assignment *else_assign =
+ ((ir_instruction *)ir->else_instructions.head)->as_assignment();
+
+ if (!then_assign || then_assign->condition ||
+ !else_assign || else_assign->condition ||
+ then_assign->write_mask != else_assign->write_mask ||
+ !then_assign->lhs->equals(else_assign->lhs))
+ return false;
+
+ ir_constant *then_rhs = then_assign->rhs->as_constant();
+ ir_constant *else_rhs = else_assign->rhs->as_constant();
+
+ if (!then_rhs || !else_rhs)
+ return false;
+
+ if ((then_rhs->is_one() || then_rhs->is_negative_one()) &&
+ (else_rhs->is_one() || else_rhs->is_negative_one())) {
+ assert(then_rhs->is_one() == else_rhs->is_negative_one());
+ assert(else_rhs->is_one() == then_rhs->is_negative_one());
+
+ then_assign->lhs->accept(this);
+ fs_reg dst = this->result;
+ dst.type = BRW_REGISTER_TYPE_D;
+ fs_reg tmp = vgrf(glsl_type::int_type);
+
+ if (brw->gen >= 6) {
+ /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
+ fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
+ */
+
+ if (then_rhs->is_negative_one()) {
+ assert(else_rhs->is_one());
+ g0.negate = true;
+ }
+
+ tmp.type = BRW_REGISTER_TYPE_W;
+ tmp.subreg_offset = 2;
+ tmp.stride = 2;
+
+ fs_inst *or_inst = emit(OR(tmp, g0, fs_reg(0x3f80)));
+ or_inst->src[1].type = BRW_REGISTER_TYPE_UW;
+
+ tmp.type = BRW_REGISTER_TYPE_D;
+ tmp.subreg_offset = 0;
+ tmp.stride = 1;
+ } else {
+ /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
+ fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
+ */
+
+ if (then_rhs->is_negative_one()) {
+ assert(else_rhs->is_one());
+ g1_6.negate = true;
+ }
+
+ emit(OR(tmp, g1_6, fs_reg(0x3f800000)));
+ }
+ emit(AND(dst, tmp, fs_reg(0xbf800000)));
+ return true;
+ }
+
+ return false;
+}
+
/**
* Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
*
*
* If src0 is an immediate value, we promote it to a temporary GRF.
*/
-void
+bool
fs_visitor::try_replace_with_sel()
{
fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
fs_inst *match = (fs_inst *) endif_inst->prev;
for (int i = 0; i < 4; i++) {
if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
- return;
+ return false;
match = (fs_inst *) match->prev;
}
*/
fs_reg src0(then_mov->src[0]);
if (src0.file == IMM) {
- src0 = fs_reg(this, glsl_type::float_type);
+ src0 = vgrf(glsl_type::float_type);
src0.type = then_mov->src[0].type;
emit(MOV(src0, then_mov->src[0]));
}
sel->predicate = if_inst->predicate;
sel->predicate_inverse = if_inst->predicate_inverse;
}
+
+ return true;
}
+
+ return false;
}
void
fs_visitor::visit(ir_if *ir)
{
- if (brw->gen < 6) {
- no16("Can't support (non-uniform) control flow on SIMD16\n");
- }
+ if (try_opt_frontfacing_ternary(ir))
+ return;
/* Don't point the annotation at the if statement, because then it plus
* the then and else blocks get printed.
emit(BRW_OPCODE_ENDIF);
- try_replace_with_sel();
+ if (!try_replace_with_sel() && brw->gen < 6) {
+ no16("Can't support (non-uniform) control flow on SIMD16\n");
+ }
}
void
location->data.binding);
/* Calculate the surface offset */
- fs_reg offset(this, glsl_type::uint_type);
+ fs_reg offset = vgrf(glsl_type::uint_type);
ir_dereference_array *deref_array = deref->as_dereference_array();
if (deref_array) {
deref_array->array_index->accept(this);
- fs_reg tmp(this, glsl_type::uint_type);
+ fs_reg tmp = vgrf(glsl_type::uint_type);
emit(MUL(tmp, this->result, fs_reg(ATOMIC_COUNTER_SIZE)));
emit(ADD(offset, tmp, fs_reg(location->data.atomic.offset)));
} else {
fs_reg dst, fs_reg offset, fs_reg src0,
fs_reg src1)
{
- bool uses_kill =
- (stage == MESA_SHADER_FRAGMENT) &&
- ((brw_wm_prog_data*) this->prog_data)->uses_kill;
int reg_width = dispatch_width / 8;
int length = 0;
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 4);
- sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
+ sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
/* Initialize the sample mask in the message header. */
emit(MOV(sources[0], fs_reg(0u)))
->force_writemask_all = true;
- if (uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
- ->force_writemask_all = true;
+ if (stage == MESA_SHADER_FRAGMENT) {
+ if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
+ emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
+ ->force_writemask_all = true;
+ } else {
+ emit(MOV(component(sources[0], 7),
+ retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
+ ->force_writemask_all = true;
+ }
} else {
+ /* The execution mask is part of the side-band information sent together with
+ * the message payload to the data port. It's implicitly ANDed with the sample
+ * mask sent in the header to compute the actual set of channels that execute
+ * the atomic operation.
+ */
+ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
emit(MOV(component(sources[0], 7),
- retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
- ->force_writemask_all = true;
+ fs_reg(0xffff)))->force_writemask_all = true;
}
length++;
/* Set the atomic operation offset. */
- sources[1] = fs_reg(this, glsl_type::uint_type);
+ sources[1] = vgrf(glsl_type::uint_type);
emit(MOV(sources[1], offset));
length++;
/* Set the atomic operation arguments. */
if (src0.file != BAD_FILE) {
- sources[length] = fs_reg(this, glsl_type::uint_type);
+ sources[length] = vgrf(glsl_type::uint_type);
emit(MOV(sources[length], src0));
length++;
}
if (src1.file != BAD_FILE) {
- sources[length] = fs_reg(this, glsl_type::uint_type);
+ sources[length] = vgrf(glsl_type::uint_type);
emit(MOV(sources[length], src1));
length++;
}
int mlen = 1 + (length - 1) * reg_width;
- fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
+ fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
BRW_REGISTER_TYPE_UD);
emit(LOAD_PAYLOAD(src_payload, sources, length));
fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
fs_reg offset)
{
- bool uses_kill =
- (stage == MESA_SHADER_FRAGMENT) &&
- ((brw_wm_prog_data*) this->prog_data)->uses_kill;
int reg_width = dispatch_width / 8;
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
- sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
+ sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
/* Initialize the sample mask in the message header. */
emit(MOV(sources[0], fs_reg(0u)))
->force_writemask_all = true;
- if (uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
- ->force_writemask_all = true;
+ if (stage == MESA_SHADER_FRAGMENT) {
+ if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
+ emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
+ ->force_writemask_all = true;
+ } else {
+ emit(MOV(component(sources[0], 7),
+ retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
+ ->force_writemask_all = true;
+ }
} else {
+ /* The execution mask is part of the side-band information sent together with
+ * the message payload to the data port. It's implicitly ANDed with the sample
+ * mask sent in the header to compute the actual set of channels that execute
+ * the atomic operation.
+ */
+ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
emit(MOV(component(sources[0], 7),
- retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
- ->force_writemask_all = true;
+ fs_reg(0xffff)))->force_writemask_all = true;
}
/* Set the surface read offset. */
- sources[1] = fs_reg(this, glsl_type::uint_type);
+ sources[1] = vgrf(glsl_type::uint_type);
emit(MOV(sources[1], offset));
int mlen = 1 + reg_width;
- fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
+ fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
BRW_REGISTER_TYPE_UD);
fs_inst *inst = emit(LOAD_PAYLOAD(src_payload, sources, 2));
int reg_width = dispatch_width / 8;
/* Everyone's favorite color. */
- emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
- emit(MOV(fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)));
- emit(MOV(fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)));
- emit(MOV(fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)));
+ const float color[4] = { 1.0, 0.0, 1.0, 0.0 };
+ for (int i = 0; i < 4; i++) {
+ emit(MOV(fs_reg(MRF, 2 + i * reg_width, BRW_REGISTER_TYPE_F,
+ dispatch_width), fs_reg(color[i])));
+ }
fs_inst *write;
- write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
- write->base_mrf = 2;
- write->mlen = 4 * reg_width;
+ write = emit(FS_OPCODE_FB_WRITE);
write->eot = true;
+ if (brw->gen >= 6) {
+ write->base_mrf = 2;
+ write->mlen = 4 * reg_width;
+ } else {
+ write->header_present = true;
+ write->base_mrf = 0;
+ write->mlen = 2 + 4 * reg_width;
+ }
+
+ /* Tell the SF we don't have any inputs. Gen4-5 require at least one
+ * varying to avoid GPU hangs, so set that.
+ */
+ brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data;
+ wm_prog_data->num_varying_inputs = brw->gen < 6 ? 1 : 0;
+ memset(wm_prog_data->urb_setup, -1,
+ sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
+
+ /* We don't have any uniforms. */
+ stage_prog_data->nr_params = 0;
+ stage_prog_data->nr_pull_params = 0;
+ stage_prog_data->curb_read_length = 0;
+ stage_prog_data->dispatch_grf_start_reg = 2;
+ wm_prog_data->dispatch_grf_start_reg_16 = 2;
+ grf_used = 1; /* Gen4-5 don't allow zero GRF blocks */
+
+ calculate_cfg();
}
/* The register location here is relative to the start of the URB
fs_visitor::emit_interpolation_setup_gen4()
{
this->current_annotation = "compute pixel centers";
- this->pixel_x = fs_reg(this, glsl_type::uint_type);
- this->pixel_y = fs_reg(this, glsl_type::uint_type);
+ this->pixel_x = vgrf(glsl_type::uint_type);
+ this->pixel_y = vgrf(glsl_type::uint_type);
this->pixel_x.type = BRW_REGISTER_TYPE_UW;
this->pixel_y.type = BRW_REGISTER_TYPE_UW;
this->current_annotation = "compute pixel deltas from v0";
if (brw->has_pln) {
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- fs_reg(this, glsl_type::vec2_type);
+ vgrf(glsl_type::vec2_type);
this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
offset(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1);
} else {
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- fs_reg(this, glsl_type::float_type);
+ vgrf(glsl_type::float_type);
this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- fs_reg(this, glsl_type::float_type);
+ vgrf(glsl_type::float_type);
}
emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
/* Compute wpos.w. It's always in our setup, since it's needed to
* interpolate the other attributes.
*/
- this->wpos_w = fs_reg(this, glsl_type::float_type);
+ this->wpos_w = vgrf(glsl_type::float_type);
emit(FS_OPCODE_LINTERP, wpos_w,
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
interp_reg(VARYING_SLOT_POS, 3));
/* Compute the pixel 1/W value from wpos.w. */
- this->pixel_w = fs_reg(this, glsl_type::float_type);
+ this->pixel_w = vgrf(glsl_type::float_type);
emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
this->current_annotation = NULL;
}
/* If the pixel centers end up used, the setup is the same as for gen4. */
this->current_annotation = "compute pixel centers";
- fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
- fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
+ fs_reg int_pixel_x = vgrf(glsl_type::uint_type);
+ fs_reg int_pixel_y = vgrf(glsl_type::uint_type);
int_pixel_x.type = BRW_REGISTER_TYPE_UW;
int_pixel_y.type = BRW_REGISTER_TYPE_UW;
emit(ADD(int_pixel_x,
* to turn the integer pixel centers into floats for their actual
* use.
*/
- this->pixel_x = fs_reg(this, glsl_type::float_type);
- this->pixel_y = fs_reg(this, glsl_type::float_type);
+ this->pixel_x = vgrf(glsl_type::float_type);
+ this->pixel_y = vgrf(glsl_type::float_type);
emit(MOV(this->pixel_x, int_pixel_x));
emit(MOV(this->pixel_y, int_pixel_y));
this->current_annotation = "compute pos.w";
this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0));
- this->wpos_w = fs_reg(this, glsl_type::float_type);
+ this->wpos_w = vgrf(glsl_type::float_type);
emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
}
int
-fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components)
+fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
+ bool use_2nd_half)
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
fs_inst *inst;
colors_enabled = (1 << components) - 1;
}
- if (dispatch_width == 8 || brw->gen >= 6) {
+ if (dispatch_width == 8 || (brw->gen >= 6 && !do_dual_src)) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1
int len = 0;
for (unsigned i = 0; i < 4; ++i) {
if (colors_enabled & (1 << i)) {
- dst[len] = fs_reg(GRF, virtual_grf_alloc(color.width / 8),
+ dst[len] = fs_reg(GRF, alloc.allocate(color.width / 8),
color.type, color.width);
inst = emit(MOV(dst[len], offset(color, i)));
inst->saturate = key->clamp_fragment_color;
len++;
}
return len;
+ } else if (brw->gen >= 6 && do_dual_src) {
+ /* SIMD16 dual source blending for gen6+.
+ *
+ * From the SNB PRM, volume 4, part 1, page 193:
+ *
+ * "The dual source render target messages only have SIMD8 forms due to
+ * maximum message length limitations. SIMD16 pixel shaders must send two
+ * of these messages to cover all of the pixels. Each message contains
+ * two colors (4 channels each) for each pixel in the message payload."
+ *
+ * So in SIMD16 dual source blending we will send 2 SIMD8 messages,
+ * each one will call this function twice (one for each color involved),
+ * so in each pass we only write 4 registers. Notice that the second
+ * SIMD8 message needs to read color data from the 2nd half of the color
+ * registers, so it needs to call this with use_2nd_half = true.
+ */
+ for (unsigned i = 0; i < 4; ++i) {
+ if (colors_enabled & (1 << i)) {
+ dst[i] = fs_reg(GRF, alloc.allocate(1), color.type);
+ inst = emit(MOV(dst[i], half(offset(color, i),
+ use_2nd_half ? 1 : 0)));
+ inst->saturate = key->clamp_fragment_color;
+ if (use_2nd_half)
+ inst->force_sechalf = true;
+ }
+ }
+ return 4;
} else {
/* pre-gen6 SIMD16 single source DP write looks like:
* m + 0: r0
*/
for (unsigned i = 0; i < 4; ++i) {
if (colors_enabled & (1 << i)) {
- dst[i] = fs_reg(GRF, virtual_grf_alloc(1), color.type);
+ dst[i] = fs_reg(GRF, alloc.allocate(1), color.type);
inst = emit(MOV(dst[i], half(offset(color, i), 0)));
inst->saturate = key->clamp_fragment_color;
- dst[i + 4] = fs_reg(GRF, virtual_grf_alloc(1), color.type);
+ dst[i + 4] = fs_reg(GRF, alloc.allocate(1), color.type);
inst = emit(MOV(dst[i + 4], half(offset(color, i), 1)));
inst->saturate = key->clamp_fragment_color;
inst->force_sechalf = true;
fs_inst *
fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1,
- fs_reg src0_alpha, unsigned components)
+ fs_reg src0_alpha, unsigned components,
+ bool use_2nd_half)
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
length += 2;
if (payload.aa_dest_stencil_reg) {
- sources[length] = fs_reg(GRF, virtual_grf_alloc(1));
+ sources[length] = fs_reg(GRF, alloc.allocate(1));
emit(MOV(sources[length],
fs_reg(brw_vec8_grf(payload.aa_dest_stencil_reg, 0))));
length++;
/* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
* it's unsinged single words, one vgrf is always 16-wide.
*/
- sources[length] = fs_reg(GRF, virtual_grf_alloc(1),
+ sources[length] = fs_reg(GRF, alloc.allocate(1),
BRW_REGISTER_TYPE_UW, 16);
emit(FS_OPCODE_SET_OMASK, sources[length], this->sample_mask);
length++;
* alpha out the pipeline to our null renderbuffer to support
* alpha-testing, alpha-to-coverage, and so on.
*/
- length += setup_color_payload(sources + length, this->outputs[0], 0);
+ length += setup_color_payload(sources + length, this->outputs[0], 0,
+ false);
} else if (color1.file == BAD_FILE) {
if (src0_alpha.file != BAD_FILE) {
- sources[length] = fs_reg(GRF, virtual_grf_alloc(reg_size),
+ sources[length] = fs_reg(GRF, alloc.allocate(reg_size),
src0_alpha.type, src0_alpha.width);
fs_inst *inst = emit(MOV(sources[length], src0_alpha));
inst->saturate = key->clamp_fragment_color;
length++;
}
- length += setup_color_payload(sources + length, color0, components);
+ length += setup_color_payload(sources + length, color0, components,
+ false);
} else {
- length += setup_color_payload(sources + length, color0, components);
- length += setup_color_payload(sources + length, color1, components);
+ length += setup_color_payload(sources + length, color0, components,
+ use_2nd_half);
+ length += setup_color_payload(sources + length, color1, components,
+ use_2nd_half);
}
if (source_depth_to_render_target) {
no16("Missing support for simd16 depth writes on gen6\n");
}
- sources[length] = fs_reg(this, glsl_type::float_type);
+ sources[length] = vgrf(glsl_type::float_type);
if (prog->OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
/* Hand over gl_FragDepth. */
assert(this->frag_depth.file != BAD_FILE);
}
if (payload.dest_depth_reg) {
- sources[length] = fs_reg(this, glsl_type::float_type);
+ sources[length] = vgrf(glsl_type::float_type);
emit(MOV(sources[length],
fs_reg(brw_vec8_grf(payload.dest_depth_reg, 0))));
length++;
/* Send from the GRF */
fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F);
load = emit(LOAD_PAYLOAD(payload, sources, length));
- payload.reg = virtual_grf_alloc(load->regs_written);
+ payload.reg = alloc.allocate(load->regs_written);
+ payload.width = dispatch_width;
load->dst = payload;
write = emit(FS_OPCODE_FB_WRITE, reg_undef, payload);
write->base_mrf = -1;
load = emit(LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F),
sources, length));
write = emit(FS_OPCODE_FB_WRITE);
+ write->exec_size = dispatch_width;
write->base_mrf = 1;
}
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- if (do_dual_src) {
- no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
- if (dispatch_width == 16)
- do_dual_src = false;
- }
-
fs_inst *inst;
if (do_dual_src) {
if (INTEL_DEBUG & DEBUG_SHADER_TIME)
inst = emit_single_fb_write(this->outputs[0], this->dual_src_output,
reg_undef, 4);
inst->target = 0;
+
+ /* SIMD16 dual source blending requires to send two SIMD8 dual source
+ * messages, where each message contains color data for 8 pixels. Color
+ * data for the first group of pixels is stored in the "lower" half of
+ * the color registers, so in SIMD16, the previous message did:
+ * m + 0: r0
+ * m + 1: g0
+ * m + 2: b0
+ * m + 3: a0
+ *
+ * Here goes the second message, which packs color data for the
+ * remaining 8 pixels. Color data for these pixels is stored in the
+ * "upper" half of the color registers, so we need to do:
+ * m + 0: r1
+ * m + 1: g1
+ * m + 2: b1
+ * m + 3: a1
+ */
+ if (dispatch_width == 16) {
+ inst = emit_single_fb_write(this->outputs[0], this->dual_src_output,
+ reg_undef, 4, true);
+ inst->target = 0;
+ }
+
prog_data->dual_src_blend = true;
} else if (key->nr_color_regions > 0) {
for (int target = 0; target < key->nr_color_regions; target++) {
current_annotation = "user clip distances";
- this->outputs[VARYING_SLOT_CLIP_DIST0] = fs_reg(this, glsl_type::vec4_type);
- this->outputs[VARYING_SLOT_CLIP_DIST1] = fs_reg(this, glsl_type::vec4_type);
+ this->outputs[VARYING_SLOT_CLIP_DIST0] = vgrf(glsl_type::vec4_type);
+ this->outputs[VARYING_SLOT_CLIP_DIST1] = vgrf(glsl_type::vec4_type);
for (int i = 0; i < key->nr_userclip_plane_consts; i++) {
fs_reg u = userplane[i];
* send to terminate the shader. */
if (vue_map->slots_valid == 0) {
- fs_reg payload = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
+ fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
fs_inst *inst = emit(MOV(payload, fs_reg(retype(brw_vec8_grf(1, 0),
BRW_REGISTER_TYPE_UD))));
inst->force_writemask_all = true;
break;
}
- zero = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
+ zero = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
emit(MOV(zero, fs_reg(0u)));
sources[length++] = zero;
* temp register and use that for the payload.
*/
for (int i = 0; i < 4; i++) {
- reg = fs_reg(GRF, virtual_grf_alloc(1), outputs[varying].type);
+ reg = fs_reg(GRF, alloc.allocate(1), outputs[varying].type);
src = offset(this->outputs[varying], i);
fs_inst *inst = emit(MOV(reg, src));
inst->saturate = true;
emit_shader_time_end();
fs_reg *payload_sources = ralloc_array(mem_ctx, fs_reg, length + 1);
- fs_reg payload = fs_reg(GRF, virtual_grf_alloc(length + 1),
+ fs_reg payload = fs_reg(GRF, alloc.allocate(length + 1),
BRW_REGISTER_TYPE_F);
/* We need WE_all on the MOV for the message header (the URB handles)
* so do a MOV to a dummy register and set force_writemask_all on the
* MOV. LOAD_PAYLOAD will preserve that.
*/
- fs_reg dummy = fs_reg(GRF, virtual_grf_alloc(1),
+ fs_reg dummy = fs_reg(GRF, alloc.allocate(1),
BRW_REGISTER_TYPE_UD);
fs_inst *inst = emit(MOV(dummy, fs_reg(retype(brw_vec8_grf(1, 0),
BRW_REGISTER_TYPE_UD))));
!reg->negate)
return;
- fs_reg temp = fs_reg(this, glsl_type::uint_type);
+ fs_reg temp = vgrf(glsl_type::uint_type);
emit(MOV(temp, *reg));
*reg = temp;
}
if (rvalue->type != glsl_type::bool_type)
return;
- fs_reg and_result = fs_reg(this, glsl_type::bool_type);
- fs_reg neg_result = fs_reg(this, glsl_type::bool_type);
+ fs_reg and_result = vgrf(glsl_type::bool_type);
+ fs_reg neg_result = vgrf(glsl_type::bool_type);
emit(AND(and_result, *reg, fs_reg(1)));
emit(MOV(neg_result, negate(and_result)));
*reg = neg_result;
this->current_annotation = NULL;
this->base_ir = NULL;
- this->virtual_grf_sizes = NULL;
- this->virtual_grf_count = 0;
- this->virtual_grf_array_size = 0;
this->virtual_grf_start = NULL;
this->virtual_grf_end = NULL;
this->live_intervals = NULL;
projects / mesa.git / blobdiff