i965/fs: No need to set compression control at the top of generate_code().

[mesa.git] / src / mesa / drivers / dri / i965 / brw_gs.c

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index edb52ac44b7e6c1661b0fccbf96a7216bb8e9e02..8f5dcf359e960bd13594ef1e805ddc6ab2910a2a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -34,7 +34,7 @@
 #include "brw_ff_gs.h"
 #include "brw_nir.h"
 #include "brw_program.h"
-#include "glsl/ir_uniform.h"
+#include "compiler/glsl/ir_uniform.h"
 
 static void
 brw_gs_debug_recompile(struct brw_context *brw,
@@ -138,9 +138,13 @@ brw_codegen_gs_prog(struct brw_context *brw,
 
    GLbitfield64 outputs_written = gp->program.Base.OutputsWritten;
 
+   prog_data.base.cull_distance_mask =
+      ((1 << gp->program.Base.CullDistanceArraySize) - 1) <<
+      gp->program.Base.ClipDistanceArraySize;
+
    brw_compute_vue_map(brw->intelScreen->devinfo,
                        &prog_data.base.vue_map, outputs_written,
-                       prog ? prog->SeparateShader : false);
+                       prog->SeparateShader);
 
    if (unlikely(INTEL_DEBUG & DEBUG_GS))
       brw_dump_ir("geometry", prog, gs, NULL);
@@ -195,7 +199,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
 }
 
 static bool
-brw_gs_state_dirty(struct brw_context *brw)
+brw_gs_state_dirty(const struct brw_context *brw)
 {
    return brw_state_dirty(brw,
                           _NEW_TEXTURE,