intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_gs_emit.c

diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c
index cbfc6aab2e4afa76e256db05f957522b7698cef9..fff3585aec434f2158acc1fdbe6ec25402f9ae1a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c
@@ -185,12 +185,10 @@ static void brw_gs_emit_vue(struct brw_gs_compile *c,
                           : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
                 0,
                 c->reg.header,
-                allocate,
-                1,             /* used */
+                allocate ? BRW_URB_WRITE_ALLOCATE_COMPLETE
+                          : BRW_URB_WRITE_EOT_COMPLETE,
                 c->nr_regs + 1, /* msg length */
                 allocate ? 1 : 0, /* response length */
-                allocate ? 0 : 1, /* eot */
-                1,             /* writes_complete */
                 0,             /* urb offset */
                 BRW_URB_SWIZZLE_NONE);
 
@@ -203,8 +201,7 @@ static void brw_gs_emit_vue(struct brw_gs_compile *c,
 /**
  * Send an FF_SYNC message to ensure that all previously spawned GS threads
  * have finished sending primitives down the pipeline, and to allocate a URB
- * entry for the first output vertex.  Only needed when intel->needs_ff_sync
- * is true.
+ * entry for the first output vertex.  Only needed on Ironlake+.
  *
  * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
  * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
@@ -230,14 +227,14 @@ static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim)
 
 void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 {
-   struct intel_context *intel = &c->func.brw->intel;
+   struct brw_context *brw = c->func.brw;
 
    brw_gs_alloc_regs(c, 4, false);
    brw_gs_initialize_header(c);
    /* Use polygons for correct edgeflag behaviour. Note that vertex 3
     * is the PV for quads, but vertex 0 for polygons:
     */
-   if (intel->needs_ff_sync)
+   if (brw->gen == 5)
       brw_gs_ff_sync(c, 1);
    brw_gs_overwrite_header_dw2(
       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
@@ -268,12 +265,12 @@ void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 
 void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 {
-   struct intel_context *intel = &c->func.brw->intel;
+   struct brw_context *brw = c->func.brw;
 
    brw_gs_alloc_regs(c, 4, false);
    brw_gs_initialize_header(c);
    
-   if (intel->needs_ff_sync)
+   if (brw->gen == 5)
       brw_gs_ff_sync(c, 1);
    brw_gs_overwrite_header_dw2(
       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
@@ -304,12 +301,12 @@ void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 
 void brw_gs_lines( struct brw_gs_compile *c )
 {
-   struct intel_context *intel = &c->func.brw->intel;
+   struct brw_context *brw = c->func.brw;
 
    brw_gs_alloc_regs(c, 2, false);
    brw_gs_initialize_header(c);
 
-   if (intel->needs_ff_sync)
+   if (brw->gen == 5)
       brw_gs_ff_sync(c, 1);
    brw_gs_overwrite_header_dw2(
       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)