intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_gs_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index 542874b7706a18aebfa14cc486963a89edfd20d4..bee0214eb65bbba9c48da18ebc2f3cac77487af8 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -36,21 +36,26 @@
 #include "brw_defines.h"
 
 static void
-brw_prepare_gs_unit(struct brw_context *brw)
+brw_upload_gs_unit(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
    struct brw_gs_unit_state *gs;
 
-   gs = brw_state_batch(brw, sizeof(*gs), 32, &brw->gs.state_offset);
+   gs = brw_state_batch(brw, AUB_TRACE_GS_STATE,
+                       sizeof(*gs), 32, &brw->gs.state_offset);
 
    memset(gs, 0, sizeof(*gs));
 
-   /* CACHE_NEW_GS_PROG */
+   /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_GS_PROG */
    if (brw->gs.prog_active) {
       gs->thread0.grf_reg_count = (ALIGN(brw->gs.prog_data->total_grf, 16) /
                                   16 - 1);
-      /* reloc */
-      gs->thread0.kernel_start_pointer = brw->gs.prog_bo->offset >> 6;
+
+      gs->thread0.kernel_start_pointer =
+        brw_program_reloc(brw,
+                          brw->gs.state_offset +
+                          offsetof(struct brw_gs_unit_state, thread0),
+                          brw->gs.prog_offset +
+                          (gs->thread0.grf_reg_count << 1)) >> 6;
 
       gs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
       gs->thread1.single_program_flow = 1;
@@ -69,16 +74,9 @@ brw_prepare_gs_unit(struct brw_context *brw)
         gs->thread4.max_threads = 1;
       else
         gs->thread4.max_threads = 0;
-
-      /* Emit GS program relocation */
-      drm_intel_bo_emit_reloc(intel->batch.bo,
-                             (brw->gs.state_offset +
-                              offsetof(struct brw_gs_unit_state, thread0)),
-                             brw->gs.prog_bo, gs->thread0.grf_reg_count << 1,
-                             I915_GEM_DOMAIN_INSTRUCTION, 0);
    }
 
-   if (intel->gen == 5)
+   if (brw->gen == 5)
       gs->thread4.rendering_enable = 1;
 
    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
@@ -91,9 +89,10 @@ const struct brw_tracked_state brw_gs_unit = {
    .dirty = {
       .mesa  = 0,
       .brw   = (BRW_NEW_BATCH |
+               BRW_NEW_PROGRAM_CACHE |
                BRW_NEW_CURBE_OFFSETS |
                BRW_NEW_URB_FENCE),
       .cache = CACHE_NEW_GS_PROG
    },
-   .prepare = brw_prepare_gs_unit,
+   .emit = brw_upload_gs_unit,
 };