i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_gs_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index cc646de7370a976149e4f9616542b33dbf736b77..f7b14066594eeb319fe42253220eb528a38e9b7b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -85,7 +85,7 @@ brw_upload_gs_unit(struct brw_context *brw)
 
    gs->gs6.max_vp_index = brw->ctx.Const.MaxViewports - 1;
 
-   brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
+   brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 }
 
 const struct brw_tracked_state brw_gs_unit = {
@@ -93,9 +93,9 @@ const struct brw_tracked_state brw_gs_unit = {
       .mesa  = 0,
       .brw   = BRW_NEW_BATCH |
                BRW_NEW_CURBE_OFFSETS |
+               BRW_NEW_FF_GS_PROG_DATA |
                BRW_NEW_PROGRAM_CACHE |
                BRW_NEW_URB_FENCE,
-      .cache = BRW_NEW_FF_GS_PROG_DATA
    },
    .emit = brw_upload_gs_unit,
 };