i965: Disable hardware blending if advanced blending is in use.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_inst.h

diff --git a/src/mesa/drivers/dri/i965/brw_inst.h b/src/mesa/drivers/dri/i965/brw_inst.h
index db05a8a5f3075c97ffd96101657a96c443c880d0..f45e56400c9dd9e928e879230351ce1568481385 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_inst.h
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -39,15 +39,6 @@
 extern "C" {
 #endif
 
-/** Maximum SEND message length */
-#define BRW_MAX_MSG_LENGTH 15
-
-/** First MRF register used by pull loads */
-#define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
-
-/** First MRF register used by spills */
-#define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
-
 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
 typedef struct brw_inst {
    uint64_t data[2];
@@ -393,6 +384,7 @@ FF(urb_per_slot_offset,
    /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
    /* 7:   */ MD(16), MD(16),
    /* 8:   */ MD(17), MD(17))
+FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8)
 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
@@ -584,6 +576,18 @@ brw_inst_imm_f(const struct brw_device_info *devinfo, const brw_inst *insn)
    return ft.f;
 }
 
+static inline double
+brw_inst_imm_df(const struct brw_device_info *devinfo, const brw_inst *insn)
+{
+   union {
+      double d;
+      uint64_t u;
+   } dt;
+   (void) devinfo;
+   dt.u = brw_inst_bits(insn, 127, 64);
+   return dt.d;
+}
+
 static inline void
 brw_inst_set_imm_d(const struct brw_device_info *devinfo,
                    brw_inst *insn, int value)
@@ -610,6 +614,19 @@ brw_inst_set_imm_f(const struct brw_device_info *devinfo,
    brw_inst_set_bits(insn, 127, 96, ft.u);
 }
 
+static inline void
+brw_inst_set_imm_df(const struct brw_device_info *devinfo,
+                    brw_inst *insn, double value)
+{
+   union {
+      double d;
+      uint64_t u;
+   } dt;
+   (void) devinfo;
+   dt.d = value;
+   brw_inst_set_bits(insn, 127, 64, dt.u);
+}
+
 /** @} */
 
 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
@@ -693,7 +710,7 @@ brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
    high %= 64;
    low %= 64;
 
-   const uint64_t mask = (1ull << (high - low + 1)) - 1;
+   const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
 
    return (inst->data[word] >> low) & mask;
 }
@@ -712,7 +729,7 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
    high %= 64;
    low %= 64;
 
-   const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
+   const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
 
    /* Make sure the supplied value actually fits in the given bitfield. */
    assert((value & (mask >> low)) == value);