i965/vec4: Simplify opt_reduce_swizzle() using the swizzle utils.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_ir_vec4.h

diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index ae024b328d903b1c82730e6ae9cfd1509d1309fa..2ac189b10439b61c9d276b801f2a5bf3721ecd98 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -58,7 +58,7 @@ public:
 
    explicit src_reg(dst_reg reg);
 
-   GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
+   unsigned swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
 
    src_reg *reladdr;
 };
@@ -111,13 +111,16 @@ public:
 
    dst_reg();
    dst_reg(register_file file, int reg);
-   dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
+   dst_reg(register_file file, int reg, const glsl_type *type,
+           unsigned writemask);
    dst_reg(struct brw_reg reg);
    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 
    explicit dst_reg(src_reg reg);
 
-   int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
+   bool equals(const dst_reg &r) const;
+
+   unsigned writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 
    src_reg *reladdr;
 };
@@ -169,6 +172,7 @@ public:
    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 
    bool is_send_from_grf();
+   unsigned regs_read(unsigned arg) const;
    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
    void reswizzle(int dst_writemask, int swizzle);
    bool can_do_source_mods(struct brw_context *brw);