i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_ir_vec4.h

diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index f11a2d21d1e5cad9e3fdb06ccac20fba27592971..fceacae0e5141bc6c5525df6e3b3ddb85e90acef 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -32,9 +32,6 @@ namespace brw {
 
 class dst_reg;
 
-unsigned
-swizzle_for_size(int size);
-
 class src_reg : public backend_reg
 {
 public:
@@ -56,9 +53,9 @@ public:
    src_reg(class vec4_visitor *v, const struct glsl_type *type);
    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
 
-   explicit src_reg(dst_reg reg);
+   explicit src_reg(const dst_reg &reg);
 
-   GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
+   unsigned swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
 
    src_reg *reladdr;
 };
@@ -86,11 +83,7 @@ static inline src_reg
 swizzle(src_reg reg, unsigned swizzle)
 {
    assert(reg.file != HW_REG);
-   reg.swizzle = BRW_SWIZZLE4(
-      BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
-      BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
-      BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
-      BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
+   reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle);
    return reg;
 }
 
@@ -102,6 +95,13 @@ negate(src_reg reg)
    return reg;
 }
 
+static inline bool
+is_uniform(const src_reg &reg)
+{
+   return (reg.file == IMM || reg.file == UNIFORM || reg.is_null()) &&
+          (!reg.reladdr || is_uniform(*reg.reladdr));
+}
+
 class dst_reg : public backend_reg
 {
 public:
@@ -111,15 +111,16 @@ public:
 
    dst_reg();
    dst_reg(register_file file, int reg);
-   dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
+   dst_reg(register_file file, int reg, const glsl_type *type,
+           unsigned writemask);
    dst_reg(struct brw_reg reg);
    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 
-   explicit dst_reg(src_reg reg);
+   explicit dst_reg(const src_reg &reg);
 
    bool equals(const dst_reg &r) const;
 
-   int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
+   unsigned writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 
    src_reg *reladdr;
 };
@@ -171,9 +172,10 @@ public:
    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 
    bool is_send_from_grf();
+   unsigned regs_read(unsigned arg) const;
    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
    void reswizzle(int dst_writemask, int swizzle);
-   bool can_do_source_mods(struct brw_context *brw);
+   bool can_do_source_mods(const struct brw_device_info *devinfo);
 
    bool reads_flag()
    {
@@ -188,6 +190,50 @@ public:
    }
 };
 
+/**
+ * Make the execution of \p inst dependent on the evaluation of a possibly
+ * inverted predicate.
+ */
+inline vec4_instruction *
+set_predicate_inv(enum brw_predicate pred, bool inverse,
+                  vec4_instruction *inst)
+{
+   inst->predicate = pred;
+   inst->predicate_inverse = inverse;
+   return inst;
+}
+
+/**
+ * Make the execution of \p inst dependent on the evaluation of a predicate.
+ */
+inline vec4_instruction *
+set_predicate(enum brw_predicate pred, vec4_instruction *inst)
+{
+   return set_predicate_inv(pred, false, inst);
+}
+
+/**
+ * Write the result of evaluating the condition given by \p mod to a flag
+ * register.
+ */
+inline vec4_instruction *
+set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst)
+{
+   inst->conditional_mod = mod;
+   return inst;
+}
+
+/**
+ * Clamp the result of \p inst to the saturation range of its destination
+ * datatype.
+ */
+inline vec4_instruction *
+set_saturate(bool saturate, vec4_instruction *inst)
+{
+   inst->saturate = saturate;
+   return inst;
+}
+
 } /* namespace brw */
 
 #endif