i965: Push down inclusion of brw_program.h.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_link.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
index fc9bee43d80cc56df968629ce44899f491c9ae3a..db0c22e3283710451efb8f06fd8d8c98a46f5b2a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -28,6 +28,7 @@
 #include "brw_fs.h"
 #include "brw_cfg.h"
 #include "brw_nir.h"
+#include "brw_program.h"
 #include "glsl/ir_optimization.h"
 #include "glsl/glsl_parser_extras.h"
 #include "main/shaderapi.h"
@@ -66,12 +67,14 @@ brw_lower_packing_builtins(struct brw_context *brw,
                            gl_shader_stage shader_type,
                            exec_list *ir)
 {
+   const struct brw_compiler *compiler = brw->intelScreen->compiler;
+
    int ops = LOWER_PACK_SNORM_2x16
            | LOWER_UNPACK_SNORM_2x16
            | LOWER_PACK_UNORM_2x16
            | LOWER_UNPACK_UNORM_2x16;
 
-   if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
+   if (compiler->scalar_stage[shader_type]) {
       ops |= LOWER_UNPACK_UNORM_4x8
            | LOWER_UNPACK_SNORM_4x8
            | LOWER_PACK_UNORM_4x8
@@ -84,7 +87,7 @@ brw_lower_packing_builtins(struct brw_context *brw,
        * lowering is needed. For SOA code, the Half2x16 ops must be
        * scalarized.
        */
-      if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
+      if (compiler->scalar_stage[shader_type]) {
          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
       }
@@ -103,6 +106,7 @@ process_glsl_ir(gl_shader_stage stage,
                 struct gl_shader *shader)
 {
    struct gl_context *ctx = &brw->ctx;
+   const struct brw_compiler *compiler = brw->intelScreen->compiler;
    const struct gl_shader_compiler_options *options =
       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 
@@ -157,13 +161,11 @@ process_glsl_ir(gl_shader_stage stage,
                  _mesa_shader_stage_to_abbrev(shader->Stage));
    }
 
-   lower_ubo_reference(shader, shader->ir);
-
    bool progress;
    do {
       progress = false;
 
-      if (is_scalar_shader_stage(brw->intelScreen->compiler, shader->Stage)) {
+      if (compiler->scalar_stage[shader->Stage]) {
          brw_do_channel_expressions(shader->ir);
          brw_do_vector_splitting(shader->ir);
       }
@@ -197,7 +199,7 @@ process_glsl_ir(gl_shader_stage stage,
    }
 }
 
-GLboolean
+extern "C" GLboolean
 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 {
    struct brw_context *brw = brw_context(ctx);
@@ -254,7 +256,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
       brw_add_texrect_params(prog);
 
       prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
-                                 is_scalar_shader_stage(compiler, stage));
+                                 compiler->scalar_stage[stage]);
 
       _mesa_reference_program(ctx, &prog, NULL);
    }