i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_meta_updownsample.c

diff --git a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
index a35b7e14f618385593adee36ddff00cac4958ce5..f39d50a69e6691ec4c27bae2ca86665e349d24a0 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
@@ -45,8 +45,10 @@
  *
  * Clobbers the current renderbuffer binding (ctx->CurrentRenderbuffer).
  */
-static GLuint
-brw_get_rb_for_first_slice(struct brw_context *brw, struct intel_mipmap_tree *mt)
+GLuint
+brw_get_rb_for_slice(struct brw_context *brw,
+                     struct intel_mipmap_tree *mt,
+                     unsigned level, unsigned layer, bool flat)
 {
    struct gl_context *ctx = &brw->ctx;
    GLuint rbo;
@@ -65,9 +67,25 @@ brw_get_rb_for_first_slice(struct brw_context *brw, struct intel_mipmap_tree *mt
    rb->Format = mt->format;
    rb->_BaseFormat = _mesa_get_format_base_format(mt->format);
 
-   rb->NumSamples = mt->num_samples;
-   rb->Width = mt->logical_width0;
-   rb->Height = mt->logical_height0;
+   /* Program takes care of msaa and mip-level access manually for stencil.
+    * The surface is also treated as Y-tiled instead of as W-tiled calling for
+    * twice the width and half the height in dimensions.
+    */
+   if (flat) {
+      const unsigned halign_stencil = 8;
+
+      rb->NumSamples = 0;
+      rb->Width = ALIGN(mt->total_width, halign_stencil) * 2;
+      rb->Height = (mt->total_height / mt->physical_depth0) / 2;
+      irb->mt_level = 0;
+   } else {
+      rb->NumSamples = mt->num_samples;
+      rb->Width = mt->logical_width0;
+      rb->Height = mt->logical_height0;
+      irb->mt_level = level;
+   }
+
+   irb->mt_layer = layer;
 
    intel_miptree_reference(&irb->mt, mt);
 
@@ -98,12 +116,12 @@ brw_meta_updownsample(struct brw_context *brw,
       blit_bit = GL_COLOR_BUFFER_BIT;
    }
 
-   intel_batchbuffer_emit_mi_flush(brw);
+   brw_emit_mi_flush(brw);
 
    _mesa_meta_begin(ctx, MESA_META_ALL);
    _mesa_GenFramebuffers(2, fbos);
-   src_rbo = brw_get_rb_for_first_slice(brw, src_mt);
-   dst_rbo = brw_get_rb_for_first_slice(brw, dst_mt);
+   src_rbo = brw_get_rb_for_slice(brw, src_mt, 0, 0, false);
+   dst_rbo = brw_get_rb_for_slice(brw, dst_mt, 0, 0, false);
    src_fbo = fbos[0];
    dst_fbo = fbos[1];
 
@@ -129,5 +147,5 @@ brw_meta_updownsample(struct brw_context *brw,
 
    _mesa_meta_end(ctx);
 
-   intel_batchbuffer_emit_mi_flush(brw);
+   brw_emit_mi_flush(brw);
 }