i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_meta_util.h

diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.h b/src/mesa/drivers/dri/i965/brw_meta_util.h
index ccd8642010c943e8e3187a97df3408b7de2719dd..dc9dff2bce3ed3bf0719df115016c6b3d760e60f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_meta_util.h
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.h
@@ -33,6 +33,8 @@ extern "C" {
 
 bool
 brw_meta_mirror_clip_and_scissor(const struct gl_context *ctx,
+                                 const struct gl_framebuffer *read_fb,
+                                 const struct gl_framebuffer *draw_fb,
                                  GLfloat *srcX0, GLfloat *srcY0,
                                  GLfloat *srcX1, GLfloat *srcY1,
                                  GLfloat *dstX0, GLfloat *dstY0,