static void
upload_pipelined_state_pointers(struct brw_context *brw)
{
- if (brw->gen == 5) {
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ if (devinfo->gen == 5) {
/* Need to flush before changing clip max threads for errata. */
BEGIN_BATCH(1);
OUT_BATCH(MI_FLUSH);
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->vs.base.state_offset);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->vs.base.state_offset);
if (brw->ff_gs.prog_active)
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->ff_gs.state_offset | 1);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->ff_gs.state_offset | 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->clip.state_offset | 1);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->sf.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->wm.base.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->cc.state_offset);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->clip.state_offset | 1);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->sf.state_offset);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->wm.base.state_offset);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->cc.state_offset);
ADVANCE_BATCH();
brw->ctx.NewDriverState |= BRW_NEW_PSP;
rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb,
bool invalidate)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
uint32_t tile_mask_x = 0, tile_mask_y = 0;
bool rebase = tile_x & 7 || tile_y & 7;
/* We didn't even have intra-tile offsets before g45. */
- rebase |= (!brw->has_surface_tile_offset && (tile_x || tile_y));
+ rebase |= (!devinfo->has_surface_tile_offset && (tile_x || tile_y));
if (rebase) {
perf_debug("HW workaround: blitting depth level %d to a temporary "
brw_workaround_depthstencil_alignment(struct brw_context *brw,
GLbitfield clear_mask)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
/* Gen6+ doesn't require the workarounds, since we always program the
* surface state at the start of the whole surface.
*/
- if (brw->gen >= 6)
+ if (devinfo->gen >= 6)
return;
/* Check if depth buffer is in depth/stencil format. If so, then it's only
void
brw_emit_depthbuffer(struct brw_context *brw)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
/* _NEW_BUFFERS */
separate_stencil = stencil_mt->format == MESA_FORMAT_S_UINT8;
/* Gen7 supports only separate stencil */
- assert(separate_stencil || brw->gen < 7);
+ assert(separate_stencil || devinfo->gen < 7);
}
/* If there's a packed depth/stencil bound to stencil only, we need to
* set to the same value. Gens after 7 implicitly always set
* Separate_Stencil_Enable; software cannot disable it.
*/
- if ((brw->gen < 7 && hiz) || brw->gen >= 7) {
+ if ((devinfo->gen < 7 && hiz) || devinfo->gen >= 7) {
assert(!_mesa_is_format_packed_depth_stencil(depth_mt->format));
}
/* Prior to Gen7, if using separate stencil, hiz must be enabled. */
- assert(brw->gen >= 7 || !separate_stencil || hiz);
+ assert(devinfo->gen >= 7 || !separate_stencil || hiz);
- assert(brw->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0);
+ assert(devinfo->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0);
assert(!hiz || depth_mt->surf.tiling == ISL_TILING_Y0);
depthbuffer_format = brw_depthbuffer_format(brw);
assert(!hiz);
assert(!separate_stencil);
- const unsigned len = (brw->is_g4x || brw->gen == 5) ? 6 : 5;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5;
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
(depthbuffer_format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
- ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
- << 27) |
+ (1 << 27) |
(depth_surface_type << 29));
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- depth_offset);
+ OUT_RELOC(depth_mt->bo, RELOC_WRITE, depth_offset);
} else {
OUT_BATCH(0);
}
((height + tile_y - 1) << 19));
OUT_BATCH(0);
- if (brw->is_g4x || brw->gen >= 5)
+ if (devinfo->is_g4x || devinfo->gen >= 5)
OUT_BATCH(tile_x | (tile_y << 16));
else
assert(tile_x == 0 && tile_y == 0);
- if (brw->gen >= 6)
+ if (devinfo->gen >= 6)
OUT_BATCH(0);
ADVANCE_BATCH();
void
brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
{
- const bool is_965 = brw->gen == 4 && !brw->is_g4x;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
- if (brw->gen >= 8 && brw->gen < 10) {
+ if (devinfo->gen >= 8 && devinfo->gen < 10) {
/* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
*
* Software must clear the COLOR_CALC_STATE Valid field in
}
}
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
* MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
*/
const unsigned dc_flush =
- brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
+ devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
/* Select the pipeline */
BEGIN_BATCH(1);
OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 |
- (brw->gen >= 9 ? (3 << 8) : 0) |
+ (devinfo->gen >= 9 ? (3 << 8) : 0) |
(pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0));
ADVANCE_BATCH();
- if (brw->gen == 7 && !brw->is_haswell &&
+ if (devinfo->gen == 7 && !devinfo->is_haswell &&
pipeline == BRW_RENDER_PIPELINE) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
void
brw_upload_invariant_state(struct brw_context *brw)
{
- const bool is_965 = brw->gen == 4 && !brw->is_g4x;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE);
brw->last_pipeline = BRW_RENDER_PIPELINE;
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
BEGIN_BATCH(3);
OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2));
OUT_BATCH(0);
void
brw_upload_state_base_address(struct brw_context *brw)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
if (brw->batch.state_base_address_emitted)
return;
* maybe this isn't required for us in particular.
*/
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
const unsigned dc_flush =
- brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
+ devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
/* Emit a render target cache flush.
*
dc_flush);
}
- if (brw->gen >= 8) {
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- int pkt_len = brw->gen >= 9 ? 19 : 16;
+ if (devinfo->gen >= 8) {
+ uint32_t mocs_wb = devinfo->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
+ int pkt_len = devinfo->gen >= 9 ? 19 : 16;
BEGIN_BATCH(pkt_len);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
/* Surface state base address: */
- OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.state_bo, 0, mocs_wb << 4 | 1);
/* Dynamic state base address: */
- OUT_RELOC64(brw->batch.bo,
- I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.state_bo, 0, mocs_wb << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
- OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->cache.bo, 0, mocs_wb << 4 | 1);
/* General state buffer size */
OUT_BATCH(0xfffff001);
/* Dynamic state buffer size */
- OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
+ OUT_BATCH(ALIGN(brw->batch.state_bo->size, 4096) | 1);
/* Indirect object upper bound */
OUT_BATCH(0xfffff001);
/* Instruction access upper bound */
OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
- if (brw->gen >= 9) {
+ if (devinfo->gen >= 9) {
OUT_BATCH(1);
OUT_BATCH(0);
OUT_BATCH(0);
}
ADVANCE_BATCH();
- } else if (brw->gen >= 6) {
- uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
+ } else if (devinfo->gen >= 6) {
+ uint8_t mocs = devinfo->gen == 7 ? GEN7_MOCS_L3 : 0;
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
* BINDING_TABLE_STATE
* SURFACE_STATE
*/
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
+ OUT_RELOC(brw->batch.state_bo, 0, 1);
/* Dynamic state base address:
* SAMPLER_STATE
* SAMPLER_BORDER_COLOR_STATE
* Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
* Disable is clear, which we rely on)
*/
- OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
- I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
+ OUT_RELOC(brw->batch.state_bo, 0, 1);
OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1); /* Instruction base address: shader kernels (incl. SIP) */
+
+ /* Instruction base address: shader kernels (incl. SIP) */
+ OUT_RELOC(brw->cache.bo, 0, 1);
OUT_BATCH(1); /* General state upper bound */
/* Dynamic state upper bound. Although the documentation says that
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(1); /* Instruction access upper bound */
ADVANCE_BATCH();
- } else if (brw->gen == 5) {
+ } else if (devinfo->gen == 5) {
BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- 1); /* Surface state base address */
+ OUT_RELOC(brw->batch.state_bo, 0, 1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1); /* Instruction base address */
+ OUT_RELOC(brw->cache.bo, 0, 1); /* Instruction base address */
OUT_BATCH(0xfffff001); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(1); /* Instruction access upper bound */
BEGIN_BATCH(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- 1); /* Surface state base address */
+ OUT_RELOC(brw->batch.state_bo, 0, 1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
ADVANCE_BATCH();
}
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_INSTRUCTION_INVALIDATE |
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
projects / mesa.git / blobdiff