i965: Calculate thread_count in brw_alloc_stage_scratch

[mesa.git] / src / mesa / drivers / dri / i965 / brw_misc_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 4ecee7fa57c34147d4732bd2717a6fecf0cb5602..53137cc4524703fc5de69d1e5a3371f8104f1c2a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -65,15 +65,15 @@ upload_pipelined_state_pointers(struct brw_context *brw)
 
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
-   OUT_RELOC(brw->batch.bo, 0, brw->vs.base.state_offset);
+   OUT_RELOC(brw->batch.state_bo, 0, brw->vs.base.state_offset);
    if (brw->ff_gs.prog_active)
-      OUT_RELOC(brw->batch.bo, 0, brw->ff_gs.state_offset | 1);
+      OUT_RELOC(brw->batch.state_bo, 0, brw->ff_gs.state_offset | 1);
    else
       OUT_BATCH(0);
-   OUT_RELOC(brw->batch.bo, 0, brw->clip.state_offset | 1);
-   OUT_RELOC(brw->batch.bo, 0, brw->sf.state_offset);
-   OUT_RELOC(brw->batch.bo, 0, brw->wm.base.state_offset);
-   OUT_RELOC(brw->batch.bo, 0, brw->cc.state_offset);
+   OUT_RELOC(brw->batch.state_bo, 0, brw->clip.state_offset | 1);
+   OUT_RELOC(brw->batch.state_bo, 0, brw->sf.state_offset);
+   OUT_RELOC(brw->batch.state_bo, 0, brw->wm.base.state_offset);
+   OUT_RELOC(brw->batch.state_bo, 0, brw->cc.state_offset);
    ADVANCE_BATCH();
 
    brw->ctx.NewDriverState |= BRW_NEW_PSP;
@@ -136,6 +136,7 @@ static bool
 rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb,
                      bool invalidate)
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
    uint32_t tile_mask_x = 0, tile_mask_y = 0;
 
@@ -156,7 +157,7 @@ rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb,
    bool rebase = tile_x & 7 || tile_y & 7;
 
    /* We didn't even have intra-tile offsets before g45. */
-   rebase |= (!brw->has_surface_tile_offset && (tile_x || tile_y));
+   rebase |= (!devinfo->has_surface_tile_offset && (tile_x || tile_y));
 
    if (rebase) {
       perf_debug("HW workaround: blitting depth level %d to a temporary "
@@ -375,7 +376,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
    assert(!separate_stencil);
 
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   const unsigned len = (brw->is_g4x || devinfo->gen == 5) ? 6 : 5;
+   const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5;
 
    BEGIN_BATCH(len);
    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
@@ -395,7 +396,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
              ((height + tile_y - 1) << 19));
    OUT_BATCH(0);
 
-   if (brw->is_g4x || devinfo->gen >= 5)
+   if (devinfo->is_g4x || devinfo->gen >= 5)
       OUT_BATCH(tile_x | (tile_y << 16));
    else
       assert(tile_x == 0 && tile_y == 0);
@@ -419,7 +420,7 @@ void
 brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
 {
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   const bool is_965 = devinfo->gen == 4 && !brw->is_g4x;
+   const bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
    const uint32_t _3DSTATE_PIPELINE_SELECT =
       is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
 
@@ -492,7 +493,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
              (pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0));
    ADVANCE_BATCH();
 
-   if (devinfo->gen == 7 && !brw->is_haswell &&
+   if (devinfo->gen == 7 && !devinfo->is_haswell &&
        pipeline == BRW_RENDER_PIPELINE) {
       /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
        * PIPELINE_SELECT [DevBWR+]":
@@ -524,7 +525,7 @@ void
 brw_upload_invariant_state(struct brw_context *brw)
 {
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   const bool is_965 = devinfo->gen == 4 && !brw->is_g4x;
+   const bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
 
    brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE);
    brw->last_pipeline = BRW_RENDER_PIPELINE;
@@ -637,9 +638,9 @@ brw_upload_state_base_address(struct brw_context *brw)
       OUT_BATCH(0);
       OUT_BATCH(mocs_wb << 16);
       /* Surface state base address: */
-      OUT_RELOC64(brw->batch.bo, 0, mocs_wb << 4 | 1);
+      OUT_RELOC64(brw->batch.state_bo, 0, mocs_wb << 4 | 1);
       /* Dynamic state base address: */
-      OUT_RELOC64(brw->batch.bo, 0, mocs_wb << 4 | 1);
+      OUT_RELOC64(brw->batch.state_bo, 0, mocs_wb << 4 | 1);
       /* Indirect object base address: MEDIA_OBJECT data */
       OUT_BATCH(mocs_wb << 4 | 1);
       OUT_BATCH(0);
@@ -649,7 +650,7 @@ brw_upload_state_base_address(struct brw_context *brw)
       /* General state buffer size */
       OUT_BATCH(0xfffff001);
       /* Dynamic state buffer size */
-      OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
+      OUT_BATCH(ALIGN(brw->batch.state_bo->size, 4096) | 1);
       /* Indirect object upper bound */
       OUT_BATCH(0xfffff001);
       /* Instruction access upper bound */
@@ -672,7 +673,7 @@ brw_upload_state_base_address(struct brw_context *brw)
        * BINDING_TABLE_STATE
        * SURFACE_STATE
        */
-       OUT_RELOC(brw->batch.bo, 0, 1);
+       OUT_RELOC(brw->batch.state_bo, 0, 1);
         /* Dynamic state base address:
         * SAMPLER_STATE
         * SAMPLER_BORDER_COLOR_STATE
@@ -683,7 +684,7 @@ brw_upload_state_base_address(struct brw_context *brw)
         * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
         * Disable is clear, which we rely on)
         */
-       OUT_RELOC(brw->batch.bo, 0, 1);
+       OUT_RELOC(brw->batch.state_bo, 0, 1);
 
        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 
@@ -704,7 +705,7 @@ brw_upload_state_base_address(struct brw_context *brw)
        BEGIN_BATCH(8);
        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
        OUT_BATCH(1); /* General state base address */
-       OUT_RELOC(brw->batch.bo, 0, 1); /* Surface state base address */
+       OUT_RELOC(brw->batch.state_bo, 0, 1); /* Surface state base address */
        OUT_BATCH(1); /* Indirect object base address */
        OUT_RELOC(brw->cache.bo, 0, 1); /* Instruction base address */
        OUT_BATCH(0xfffff001); /* General state upper bound */
@@ -715,7 +716,7 @@ brw_upload_state_base_address(struct brw_context *brw)
        BEGIN_BATCH(6);
        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
        OUT_BATCH(1); /* General state base address */
-       OUT_RELOC(brw->batch.bo, 0, 1); /* Surface state base address */
+       OUT_RELOC(brw->batch.state_bo, 0, 1); /* Surface state base address */
        OUT_BATCH(1); /* Indirect object base address */
        OUT_BATCH(1); /* General state upper bound */
        OUT_BATCH(1); /* Indirect object upper bound */