static void
upload_pipelined_state_pointers(struct brw_context *brw)
{
- if (brw->gen == 5) {
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ if (devinfo->gen == 5) {
/* Need to flush before changing clip max threads for errata. */
BEGIN_BATCH(1);
OUT_BATCH(MI_FLUSH);
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->vs.base.state_offset);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->vs.base.state_offset);
if (brw->ff_gs.prog_active)
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->ff_gs.state_offset | 1);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->ff_gs.state_offset | 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->clip.state_offset | 1);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->sf.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->wm.base.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->cc.state_offset);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->clip.state_offset | 1);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->sf.state_offset);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->wm.base.state_offset);
+ OUT_RELOC(brw->batch.state_bo, 0, brw->cc.state_offset);
ADVANCE_BATCH();
brw->ctx.NewDriverState |= BRW_NEW_PSP;
return brw_depth_format(brw, drb->mt->format);
}
-/**
- * Returns the mask of how many bits of x and y must be handled through the
- * depthbuffer's draw offset x and y fields.
- *
- * The draw offset x/y field of the depthbuffer packet is unfortunately shared
- * between the depth, hiz, and stencil buffers. Because it can be hard to get
- * all 3 to agree on this value, we want to do as much drawing offset
- * adjustment as possible by moving the base offset of the 3 buffers, which is
- * restricted to tile boundaries.
- *
- * For each buffer, the remainder must be applied through the x/y draw offset.
- * This returns the worst-case mask of the low bits that have to go into the
- * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
- * mask, then we're in trouble.
- */
-static void
-brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
- uint32_t depth_level,
- uint32_t depth_layer,
- struct intel_mipmap_tree *stencil_mt,
- uint32_t *out_tile_mask_x,
- uint32_t *out_tile_mask_y)
-{
- uint32_t tile_mask_x = 0, tile_mask_y = 0;
-
- if (depth_mt) {
- intel_get_tile_masks(depth_mt->tiling,
- depth_mt->cpp,
- &tile_mask_x, &tile_mask_y);
- assert(!intel_miptree_level_has_hiz(depth_mt, depth_level));
- }
-
- if (stencil_mt) {
- if (stencil_mt->stencil_mt)
- stencil_mt = stencil_mt->stencil_mt;
-
- if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
- /* Separate stencil buffer uses 64x64 tiles. */
- tile_mask_x |= 63;
- tile_mask_y |= 63;
- } else {
- uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
- intel_get_tile_masks(stencil_mt->tiling,
- stencil_mt->cpp,
- &stencil_tile_mask_x,
- &stencil_tile_mask_y);
-
- tile_mask_x |= stencil_tile_mask_x;
- tile_mask_y |= stencil_tile_mask_y;
- }
- }
-
- *out_tile_mask_x = tile_mask_x;
- *out_tile_mask_y = tile_mask_y;
-}
-
static struct intel_mipmap_tree *
get_stencil_miptree(struct intel_renderbuffer *irb)
{
return NULL;
if (irb->mt->stencil_mt)
return irb->mt->stencil_mt;
- return irb->mt;
+ return intel_renderbuffer_get_mt(irb);
+}
+
+static bool
+rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb,
+ bool invalidate)
+{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ struct gl_context *ctx = &brw->ctx;
+ uint32_t tile_mask_x = 0, tile_mask_y = 0;
+
+ intel_get_tile_masks(irb->mt->surf.tiling, irb->mt->cpp,
+ &tile_mask_x, &tile_mask_y);
+ assert(!intel_miptree_level_has_hiz(irb->mt, irb->mt_level));
+
+ uint32_t tile_x = irb->draw_x & tile_mask_x;
+ uint32_t tile_y = irb->draw_y & tile_mask_y;
+
+ /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
+ * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
+ * Coordinate Offset X/Y":
+ *
+ * "The 3 LSBs of both offsets must be zero to ensure correct
+ * alignment"
+ */
+ bool rebase = tile_x & 7 || tile_y & 7;
+
+ /* We didn't even have intra-tile offsets before g45. */
+ rebase |= (!devinfo->has_surface_tile_offset && (tile_x || tile_y));
+
+ if (rebase) {
+ perf_debug("HW workaround: blitting depth level %d to a temporary "
+ "to fix alignment (depth tile offset %d,%d)\n",
+ irb->mt_level, tile_x, tile_y);
+ intel_renderbuffer_move_to_temp(brw, irb, invalidate);
+
+ /* There is now only single slice miptree. */
+ brw->depthstencil.tile_x = 0;
+ brw->depthstencil.tile_y = 0;
+ brw->depthstencil.depth_offset = 0;
+ return true;
+ }
+
+ /* While we just tried to get everything aligned, we may have failed to do
+ * so in the case of rendering to array or 3D textures, where nonzero faces
+ * will still have an offset post-rebase. At least give an informative
+ * warning.
+ */
+ WARN_ONCE((tile_x & 7) || (tile_y & 7),
+ "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
+ "Truncating offset (%u:%u), bad rendering may occur.\n",
+ tile_x, tile_y);
+ tile_x &= ~7;
+ tile_y &= ~7;
+
+ brw->depthstencil.tile_x = tile_x;
+ brw->depthstencil.tile_y = tile_y;
+ brw->depthstencil.depth_offset = intel_miptree_get_aligned_offset(
+ irb->mt,
+ irb->draw_x & ~tile_mask_x,
+ irb->draw_y & ~tile_mask_y);
+
+ return false;
}
void
brw_workaround_depthstencil_alignment(struct brw_context *brw,
GLbitfield clear_mask)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
- bool rebase_depth = false;
- bool rebase_stencil = false;
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
struct intel_mipmap_tree *depth_mt = NULL;
- struct intel_mipmap_tree *stencil_mt = get_stencil_miptree(stencil_irb);
- uint32_t tile_x = 0, tile_y = 0, stencil_tile_x = 0, stencil_tile_y = 0;
- uint32_t stencil_draw_x = 0, stencil_draw_y = 0;
bool invalidate_depth = clear_mask & BUFFER_BIT_DEPTH;
bool invalidate_stencil = clear_mask & BUFFER_BIT_STENCIL;
brw->depthstencil.tile_x = 0;
brw->depthstencil.tile_y = 0;
brw->depthstencil.depth_offset = 0;
- brw->depthstencil.depth_mt = NULL;
- brw->depthstencil.stencil_mt = NULL;
- if (depth_irb)
- brw->depthstencil.depth_mt = depth_mt;
- if (stencil_irb)
- brw->depthstencil.stencil_mt = get_stencil_miptree(stencil_irb);
/* Gen6+ doesn't require the workarounds, since we always program the
* surface state at the start of the whole surface.
*/
- if (brw->gen >= 6)
+ if (devinfo->gen >= 6)
return;
/* Check if depth buffer is in depth/stencil format. If so, then it's only
- * safe to invalidate it if we're also clearing stencil, and both depth_irb
- * and stencil_irb point to the same miptree.
- *
- * Note: it's not sufficient to check for the case where
- * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
- * because this fails to catch depth/stencil buffers on hardware that uses
- * separate stencil. To catch that case, we check whether
- * depth_mt->stencil_mt is non-NULL.
+ * safe to invalidate it if we're also clearing stencil.
*/
if (depth_irb && invalidate_depth &&
- (_mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL ||
- depth_mt->stencil_mt)) {
- invalidate_depth = invalidate_stencil && depth_irb && stencil_irb
- && depth_irb->mt == stencil_irb->mt;
- }
-
- uint32_t tile_mask_x, tile_mask_y;
- brw_get_depthstencil_tile_masks(depth_mt,
- depth_mt ? depth_irb->mt_level : 0,
- depth_mt ? depth_irb->mt_layer : 0,
- stencil_mt,
- &tile_mask_x, &tile_mask_y);
+ _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL)
+ invalidate_depth = invalidate_stencil && stencil_irb;
if (depth_irb) {
- tile_x = depth_irb->draw_x & tile_mask_x;
- tile_y = depth_irb->draw_y & tile_mask_y;
-
- /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
- * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
- * Coordinate Offset X/Y":
- *
- * "The 3 LSBs of both offsets must be zero to ensure correct
- * alignment"
- */
- if (tile_x & 7 || tile_y & 7)
- rebase_depth = true;
-
- /* We didn't even have intra-tile offsets before g45. */
- if (!brw->has_surface_tile_offset) {
- if (tile_x || tile_y)
- rebase_depth = true;
- }
-
- if (rebase_depth) {
- perf_debug("HW workaround: blitting depth level %d to a temporary "
- "to fix alignment (depth tile offset %d,%d)\n",
- depth_irb->mt_level, tile_x, tile_y);
- intel_renderbuffer_move_to_temp(brw, depth_irb, invalidate_depth);
+ if (rebase_depth_stencil(brw, depth_irb, invalidate_depth)) {
/* In the case of stencil_irb being the same packed depth/stencil
* texture but not the same rb, make it point at our rebased mt, too.
*/
intel_miptree_reference(&stencil_irb->mt, depth_irb->mt);
intel_renderbuffer_set_draw_offset(stencil_irb);
}
-
- stencil_mt = get_stencil_miptree(stencil_irb);
-
- tile_x = depth_irb->draw_x & tile_mask_x;
- tile_y = depth_irb->draw_y & tile_mask_y;
}
if (stencil_irb) {
}
}
- /* If we have (just) stencil, check it for ignored low bits as well */
- if (!depth_irb && stencil_irb) {
- intel_miptree_get_image_offset(stencil_mt,
- stencil_irb->mt_level,
- stencil_irb->mt_layer,
- &stencil_draw_x, &stencil_draw_y);
- stencil_tile_x = stencil_draw_x & tile_mask_x;
- stencil_tile_y = stencil_draw_y & tile_mask_y;
-
- if (stencil_tile_x & 7 || stencil_tile_y & 7)
- rebase_stencil = true;
-
- if (!brw->has_surface_tile_offset) {
- if (stencil_tile_x || stencil_tile_y)
- rebase_stencil = true;
- }
- }
-
- if (rebase_stencil) {
- /* If stencil needs rebase, there isn't a depth attachment and the
- * combined depth-stencil is used for stencil only. Otherwise in case
- * depth attachment is present both stencil and depth point to the same
- * miptree. Rebase of depth is considered first updating stencil
- * attachment accordingly - hence stencil is rebased only if there is no
- * depth attachment.
- */
- assert(!depth_irb);
- perf_debug("HW workaround: blitting stencil level %d to a temporary "
- "to fix alignment (stencil tile offset %d,%d)\n",
- stencil_irb->mt_level, stencil_tile_x, stencil_tile_y);
-
- intel_renderbuffer_move_to_temp(brw, stencil_irb, invalidate_stencil);
- stencil_mt = get_stencil_miptree(stencil_irb);
-
- intel_miptree_get_image_offset(stencil_mt,
- stencil_irb->mt_level,
- stencil_irb->mt_layer,
- &stencil_draw_x, &stencil_draw_y);
- stencil_tile_x = stencil_draw_x & tile_mask_x;
- stencil_tile_y = stencil_draw_y & tile_mask_y;
- }
-
- if (!depth_irb) {
- tile_x = stencil_tile_x;
- tile_y = stencil_tile_y;
- }
-
- /* While we just tried to get everything aligned, we may have failed to do
- * so in the case of rendering to array or 3D textures, where nonzero faces
- * will still have an offset post-rebase. At least give an informative
- * warning.
- */
- WARN_ONCE((tile_x & 7) || (tile_y & 7),
- "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
- "Truncating offset, bad rendering may occur.\n");
- tile_x &= ~7;
- tile_y &= ~7;
-
- /* Now, after rebasing, save off the new dephtstencil state so the hardware
- * packets can just dereference that without re-calculating tile offsets.
- */
- brw->depthstencil.tile_x = tile_x;
- brw->depthstencil.tile_y = tile_y;
- if (depth_irb) {
- depth_mt = depth_irb->mt;
- brw->depthstencil.depth_mt = depth_mt;
- brw->depthstencil.depth_offset =
- intel_miptree_get_aligned_offset(depth_mt,
- depth_irb->draw_x & ~tile_mask_x,
- depth_irb->draw_y & ~tile_mask_y);
- assert(!intel_renderbuffer_has_hiz(depth_irb));
- }
- if (stencil_irb) {
- stencil_mt = get_stencil_miptree(stencil_irb);
-
- brw->depthstencil.stencil_mt = stencil_mt;
- assert(stencil_mt->format != MESA_FORMAT_S_UINT8);
-
- if (!depth_irb) {
- brw->depthstencil.depth_offset =
- intel_miptree_get_aligned_offset(
- stencil_mt,
- stencil_irb->draw_x & ~tile_mask_x,
- stencil_irb->draw_y & ~tile_mask_y);
- }
- }
+ /* If there is no depth attachment, consider if stencil needs rebase. */
+ if (!depth_irb && stencil_irb)
+ rebase_depth_stencil(brw, stencil_irb, invalidate_stencil);
}
void
brw_emit_depthbuffer(struct brw_context *brw)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
- struct intel_mipmap_tree *depth_mt = brw->depthstencil.depth_mt;
- struct intel_mipmap_tree *stencil_mt = brw->depthstencil.stencil_mt;
+ struct intel_mipmap_tree *depth_mt = intel_renderbuffer_get_mt(depth_irb);
+ struct intel_mipmap_tree *stencil_mt = get_stencil_miptree(stencil_irb);
uint32_t tile_x = brw->depthstencil.tile_x;
uint32_t tile_y = brw->depthstencil.tile_y;
bool hiz = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
separate_stencil = stencil_mt->format == MESA_FORMAT_S_UINT8;
/* Gen7 supports only separate stencil */
- assert(separate_stencil || brw->gen < 7);
+ assert(separate_stencil || devinfo->gen < 7);
}
/* If there's a packed depth/stencil bound to stencil only, we need to
* set to the same value. Gens after 7 implicitly always set
* Separate_Stencil_Enable; software cannot disable it.
*/
- if ((brw->gen < 7 && hiz) || brw->gen >= 7) {
+ if ((devinfo->gen < 7 && hiz) || devinfo->gen >= 7) {
assert(!_mesa_is_format_packed_depth_stencil(depth_mt->format));
}
/* Prior to Gen7, if using separate stencil, hiz must be enabled. */
- assert(brw->gen >= 7 || !separate_stencil || hiz);
+ assert(devinfo->gen >= 7 || !separate_stencil || hiz);
- assert(brw->gen < 6 || depth_mt->tiling == I915_TILING_Y);
- assert(!hiz || depth_mt->tiling == I915_TILING_Y);
+ assert(devinfo->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0);
+ assert(!hiz || depth_mt->surf.tiling == ISL_TILING_Y0);
depthbuffer_format = brw_depthbuffer_format(brw);
depth_surface_type = BRW_SURFACE_2D;
assert(!hiz);
assert(!separate_stencil);
- const unsigned len = (brw->is_g4x || brw->gen == 5) ? 6 : 5;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5;
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
- OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
+ OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
(depthbuffer_format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
- ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1)
- << 27) |
+ (1 << 27) |
(depth_surface_type << 29));
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- depth_offset);
+ OUT_RELOC(depth_mt->bo, RELOC_WRITE, depth_offset);
} else {
OUT_BATCH(0);
}
((height + tile_y - 1) << 19));
OUT_BATCH(0);
- if (brw->is_g4x || brw->gen >= 5)
+ if (devinfo->is_g4x || devinfo->gen >= 5)
OUT_BATCH(tile_x | (tile_y << 16));
else
assert(tile_x == 0 && tile_y == 0);
- if (brw->gen >= 6)
+ if (devinfo->gen >= 6)
OUT_BATCH(0);
ADVANCE_BATCH();
void
brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
{
- const bool is_965 = brw->gen == 4 && !brw->is_g4x;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
- if (brw->gen >= 8 && brw->gen < 10) {
+ if (devinfo->gen >= 8 && devinfo->gen < 10) {
/* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
*
* Software must clear the COLOR_CALC_STATE Valid field in
}
}
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
* MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
*/
const unsigned dc_flush =
- brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
+ devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
/* Select the pipeline */
BEGIN_BATCH(1);
OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 |
- (brw->gen >= 9 ? (3 << 8) : 0) |
+ (devinfo->gen >= 9 ? (3 << 8) : 0) |
(pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0));
ADVANCE_BATCH();
- if (brw->gen == 7 && !brw->is_haswell &&
+ if (devinfo->gen == 7 && !devinfo->is_haswell &&
pipeline == BRW_RENDER_PIPELINE) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
void
brw_upload_invariant_state(struct brw_context *brw)
{
- const bool is_965 = brw->gen == 4 && !brw->is_g4x;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE);
brw->last_pipeline = BRW_RENDER_PIPELINE;
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
BEGIN_BATCH(3);
OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2));
OUT_BATCH(0);
void
brw_upload_state_base_address(struct brw_context *brw)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
if (brw->batch.state_base_address_emitted)
return;
* maybe this isn't required for us in particular.
*/
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
const unsigned dc_flush =
- brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
+ devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
/* Emit a render target cache flush.
*
dc_flush);
}
- if (brw->gen >= 8) {
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- int pkt_len = brw->gen >= 9 ? 19 : 16;
+ if (devinfo->gen >= 8) {
+ uint32_t mocs_wb = devinfo->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
+ int pkt_len = devinfo->gen >= 9 ? 19 : 16;
BEGIN_BATCH(pkt_len);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
/* Surface state base address: */
- OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.state_bo, 0, mocs_wb << 4 | 1);
/* Dynamic state base address: */
- OUT_RELOC64(brw->batch.bo,
- I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.state_bo, 0, mocs_wb << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
- OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->cache.bo, 0, mocs_wb << 4 | 1);
/* General state buffer size */
OUT_BATCH(0xfffff001);
/* Dynamic state buffer size */
- OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
+ OUT_BATCH(ALIGN(brw->batch.state_bo->size, 4096) | 1);
/* Indirect object upper bound */
OUT_BATCH(0xfffff001);
/* Instruction access upper bound */
OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
- if (brw->gen >= 9) {
+ if (devinfo->gen >= 9) {
OUT_BATCH(1);
OUT_BATCH(0);
OUT_BATCH(0);
}
ADVANCE_BATCH();
- } else if (brw->gen >= 6) {
- uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
+ } else if (devinfo->gen >= 6) {
+ uint8_t mocs = devinfo->gen == 7 ? GEN7_MOCS_L3 : 0;
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
* BINDING_TABLE_STATE
* SURFACE_STATE
*/
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
+ OUT_RELOC(brw->batch.state_bo, 0, 1);
/* Dynamic state base address:
* SAMPLER_STATE
* SAMPLER_BORDER_COLOR_STATE
* Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
* Disable is clear, which we rely on)
*/
- OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
- I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
+ OUT_RELOC(brw->batch.state_bo, 0, 1);
OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1); /* Instruction base address: shader kernels (incl. SIP) */
+
+ /* Instruction base address: shader kernels (incl. SIP) */
+ OUT_RELOC(brw->cache.bo, 0, 1);
OUT_BATCH(1); /* General state upper bound */
/* Dynamic state upper bound. Although the documentation says that
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(1); /* Instruction access upper bound */
ADVANCE_BATCH();
- } else if (brw->gen == 5) {
+ } else if (devinfo->gen == 5) {
BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- 1); /* Surface state base address */
+ OUT_RELOC(brw->batch.state_bo, 0, 1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1); /* Instruction base address */
+ OUT_RELOC(brw->cache.bo, 0, 1); /* Instruction base address */
OUT_BATCH(0xfffff001); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(1); /* Instruction access upper bound */
BEGIN_BATCH(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- 1); /* Surface state base address */
+ OUT_RELOC(brw->batch.state_bo, 0, 1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
ADVANCE_BATCH();
}
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_INSTRUCTION_INVALIDATE |
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
projects / mesa.git / blobdiff