#include "intel_batchbuffer.h"
+#include "intel_fbo.h"
#include "intel_regions.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
-
-
-
-
-/***********************************************************************
- * Blend color
- */
-
-static void upload_blend_constant_color(struct brw_context *brw)
-{
- GLcontext *ctx = &brw->intel.ctx;
- struct brw_blend_constant_color bcc;
-
- memset(&bcc, 0, sizeof(bcc));
- bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR;
- bcc.header.length = sizeof(bcc)/4-2;
- bcc.blend_constant_color[0] = ctx->Color.BlendColor[0];
- bcc.blend_constant_color[1] = ctx->Color.BlendColor[1];
- bcc.blend_constant_color[2] = ctx->Color.BlendColor[2];
- bcc.blend_constant_color[3] = ctx->Color.BlendColor[3];
-
- BRW_CACHED_BATCH_STRUCT(brw, &bcc);
-}
-
-
-const struct brw_tracked_state brw_blend_constant_color = {
- .dirty = {
- .mesa = _NEW_COLOR,
- .brw = BRW_NEW_CONTEXT,
- .cache = 0
- },
- .emit = upload_blend_constant_color
-};
-
/* Constant single cliprect for framebuffer object or DRI2 drawing */
static void upload_drawing_rect(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
- GLcontext *ctx = &intel->ctx;
+ struct gl_context *ctx = &intel->ctx;
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
struct intel_context *intel = &brw->intel;
BEGIN_BATCH(6);
- OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
+ OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
OUT_BATCH(brw->vs.bind_bo_offset);
OUT_BATCH(0); /* gs */
OUT_BATCH(0); /* clip */
const struct brw_tracked_state brw_binding_table_pointers = {
.dirty = {
.mesa = 0,
- .brw = BRW_NEW_BATCH | BRW_NEW_BINDING_TABLE,
+ .brw = BRW_NEW_BATCH
+ | BRW_NEW_VS_BINDING_TABLE
+ | BRW_NEW_GS_BINDING_TABLE
+ | BRW_NEW_PS_BINDING_TABLE,
.cache = 0,
},
.emit = upload_binding_table_pointers,
struct intel_context *intel = &brw->intel;
BEGIN_BATCH(4);
- OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 |
+ OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
GEN6_BINDING_TABLE_MODIFY_VS |
GEN6_BINDING_TABLE_MODIFY_GS |
GEN6_BINDING_TABLE_MODIFY_PS |
const struct brw_tracked_state gen6_binding_table_pointers = {
.dirty = {
.mesa = 0,
- .brw = BRW_NEW_BATCH | BRW_NEW_BINDING_TABLE,
+ .brw = BRW_NEW_BATCH
+ | BRW_NEW_VS_BINDING_TABLE
+ | BRW_NEW_GS_BINDING_TABLE
+ | BRW_NEW_PS_BINDING_TABLE,
.cache = 0,
},
.emit = upload_gen6_binding_table_pointers,
}
BEGIN_BATCH(7);
- OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
+ OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ brw->vs.state_offset);
if (brw->gs.prog_active)
- OUT_RELOC(brw->gs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+ OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ brw->gs.state_offset | 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
- OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ brw->clip.state_offset | 1);
+ OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ brw->sf.state_offset);
+ OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ brw->wm.state_offset);
+ OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->cc.state_offset);
ADVANCE_BATCH();
brw->state.dirty.brw |= BRW_NEW_PSP;
}
-
-static void prepare_psp_urb_cbs(struct brw_context *brw)
-{
- brw_add_validated_bo(brw, brw->vs.state_bo);
- brw_add_validated_bo(brw, brw->gs.state_bo);
- brw_add_validated_bo(brw, brw->clip.state_bo);
- brw_add_validated_bo(brw, brw->sf.state_bo);
- brw_add_validated_bo(brw, brw->wm.state_bo);
-}
-
static void upload_psp_urb_cbs(struct brw_context *brw )
{
upload_pipelined_state_pointers(brw);
CACHE_NEW_WM_UNIT |
CACHE_NEW_CC_UNIT)
},
- .prepare = prepare_psp_urb_cbs,
.emit = upload_psp_urb_cbs,
};
static void prepare_depthbuffer(struct brw_context *brw)
{
- struct intel_region *region = brw->state.depth_region;
-
- if (region != NULL)
- brw_add_validated_bo(brw, region->buffer);
+ struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &intel->ctx;
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+
+ if (drb)
+ brw_add_validated_bo(brw, drb->region->buffer);
+ if (srb)
+ brw_add_validated_bo(brw, srb->region->buffer);
}
static void emit_depthbuffer(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
- struct intel_region *region = brw->state.depth_region;
+ struct gl_context *ctx = &intel->ctx;
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ /* _NEW_BUFFERS */
+ struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
unsigned int len;
+ /* If we're combined depth stencil but no depth is attached, look
+ * up stencil.
+ */
+ if (!irb)
+ irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+
if (intel->gen >= 6)
len = 7;
else if (intel->is_g4x || intel->gen == 5)
else
len = 5;
- if (region == NULL) {
+ if (!irb) {
BEGIN_BATCH(len);
- OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
+ OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
(BRW_SURFACE_NULL << 29));
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
+ struct intel_region *region = irb->region;
unsigned int format;
switch (region->cpp) {
}
assert(region->tiling != I915_TILING_X);
- if (intel->gen >= 6)
- assert(region->tiling != I915_TILING_NONE);
+ assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
BEGIN_BATCH(len);
- OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
+ OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH(((region->pitch * region->cpp) - 1) |
(format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
- ((region->pitch - 1) << 6) |
+ ((region->width - 1) << 6) |
((region->height - 1) << 19));
OUT_BATCH(0);
/* Initialize it for safety. */
if (intel->gen >= 6) {
BEGIN_BATCH(2);
- OUT_BATCH(CMD_3D_CLEAR_PARAMS << 16 | (2 - 2));
+ OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
}
const struct brw_tracked_state brw_depthbuffer = {
.dirty = {
- .mesa = 0,
- .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH,
+ .mesa = _NEW_BUFFERS,
+ .brw = BRW_NEW_BATCH,
.cache = 0,
},
.prepare = prepare_depthbuffer,
static void upload_polygon_stipple(struct brw_context *brw)
{
- GLcontext *ctx = &brw->intel.ctx;
- struct brw_polygon_stipple bps;
+ struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &brw->intel.ctx;
GLuint i;
- memset(&bps, 0, sizeof(bps));
- bps.header.opcode = CMD_POLY_STIPPLE_PATTERN;
- bps.header.length = sizeof(bps)/4-2;
+ if (!ctx->Polygon.StippleFlag)
+ return;
+
+ BEGIN_BATCH(33);
+ OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
/* Polygon stipple is provided in OpenGL order, i.e. bottom
* row first. If we're rendering to a window (i.e. the
*/
if (ctx->DrawBuffer->Name == 0) {
for (i = 0; i < 32; i++)
- bps.stipple[i] = ctx->PolygonStipple[31 - i]; /* invert */
+ OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
}
else {
for (i = 0; i < 32; i++)
- bps.stipple[i] = ctx->PolygonStipple[i]; /* don't invert */
+ OUT_BATCH(ctx->PolygonStipple[i]);
}
-
- BRW_CACHED_BATCH_STRUCT(brw, &bps);
+ CACHED_BATCH();
}
const struct brw_tracked_state brw_polygon_stipple = {
static void upload_polygon_stipple_offset(struct brw_context *brw)
{
- GLcontext *ctx = &brw->intel.ctx;
- struct brw_polygon_stipple_offset bpso;
+ struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &brw->intel.ctx;
- memset(&bpso, 0, sizeof(bpso));
- bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
- bpso.header.length = sizeof(bpso)/4-2;
+ if (!ctx->Polygon.StippleFlag)
+ return;
+
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
/* If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
* we have to invert the Y axis in order to match the OpenGL
* system works just fine, and there's no window system to
* worry about.
*/
- if (brw->intel.ctx.DrawBuffer->Name == 0) {
- bpso.bits0.x_offset = 0;
- bpso.bits0.y_offset = (32 - (ctx->DrawBuffer->Height & 31)) & 31;
- }
- else {
- bpso.bits0.y_offset = 0;
- bpso.bits0.x_offset = 0;
- }
-
- BRW_CACHED_BATCH_STRUCT(brw, &bpso);
+ if (brw->intel.ctx.DrawBuffer->Name == 0)
+ OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
+ else
+ OUT_BATCH(0);
+ CACHED_BATCH();
}
#define _NEW_WINDOW_POS 0x40000000
const struct brw_tracked_state brw_polygon_stipple_offset = {
.dirty = {
- .mesa = _NEW_WINDOW_POS,
+ .mesa = _NEW_WINDOW_POS | _NEW_POLYGONSTIPPLE,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
*/
static void upload_aa_line_parameters(struct brw_context *brw)
{
- struct brw_aa_line_parameters balp;
+ struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &brw->intel.ctx;
- if (!brw->has_aa_line_parameters)
+ if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
return;
+ OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
/* use legacy aa line coverage computation */
- memset(&balp, 0, sizeof(balp));
- balp.header.opcode = CMD_AA_LINE_PARAMETERS;
- balp.header.length = sizeof(balp) / 4 - 2;
-
- BRW_CACHED_BATCH_STRUCT(brw, &balp);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ CACHED_BATCH();
}
const struct brw_tracked_state brw_aa_line_parameters = {
.dirty = {
- .mesa = 0,
+ .mesa = _NEW_LINE,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
static void upload_line_stipple(struct brw_context *brw)
{
- GLcontext *ctx = &brw->intel.ctx;
- struct brw_line_stipple bls;
+ struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &brw->intel.ctx;
GLfloat tmp;
GLint tmpi;
- memset(&bls, 0, sizeof(bls));
- bls.header.opcode = CMD_LINE_STIPPLE_PATTERN;
- bls.header.length = sizeof(bls)/4 - 2;
-
- bls.bits0.pattern = ctx->Line.StipplePattern;
- bls.bits1.repeat_count = ctx->Line.StippleFactor;
+ if (!ctx->Line.StippleFlag)
+ return;
+ BEGIN_BATCH(3);
+ OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
+ OUT_BATCH(ctx->Line.StipplePattern);
tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
tmpi = tmp * (1<<13);
-
-
- bls.bits1.inverse_repeat_count = tmpi;
-
- BRW_CACHED_BATCH_STRUCT(brw, &bls);
+ OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
+ CACHED_BATCH();
}
const struct brw_tracked_state brw_line_stipple = {
/* Disable depth offset clamping.
*/
- gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP;
+ gdo.header.opcode = _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP;
gdo.header.length = sizeof(gdo)/4 - 2;
gdo.depth_offset_clamp = 0.0;
if (intel->gen >= 6) {
int i;
+ int len = intel->gen >= 7 ? 4 : 3;
- intel_batchbuffer_emit_mi_flush(intel->batch);
-
- BEGIN_BATCH(3);
- OUT_BATCH(CMD_3D_MULTISAMPLE << 16 | (3 - 2));
+ BEGIN_BATCH(len);
+ OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
MS_NUMSAMPLES_1);
OUT_BATCH(0); /* positions for 4/8-sample */
+ if (intel->gen >= 7)
+ OUT_BATCH(0);
ADVANCE_BATCH();
BEGIN_BATCH(2);
- OUT_BATCH(CMD_3D_SAMPLE_MASK << 16 | (2 - 2));
+ OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
OUT_BATCH(1);
ADVANCE_BATCH();
for (i = 0; i < 4; i++) {
BEGIN_BATCH(4);
- OUT_BATCH(CMD_GS_SVB_INDEX << 16 | (4 - 2));
+ OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
OUT_BATCH(i << SVB_INDEX_SHIFT);
OUT_BATCH(0);
OUT_BATCH(0xffffffff);
memset(&vfs, 0, sizeof(vfs));
vfs.opcode = brw->CMD_VF_STATISTICS;
- if (INTEL_DEBUG & DEBUG_STATS)
+ if (unlikely(INTEL_DEBUG & DEBUG_STATS))
vfs.statistics_enable = 1;
BRW_BATCH_STRUCT(brw, &vfs);
if (intel->gen >= 6) {
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
- OUT_BATCH(1); /* General state base address */
- OUT_RELOC(intel->batch->buf, I915_GEM_DOMAIN_SAMPLER, 0,
- 1); /* Surface state base address */
- OUT_BATCH(1); /* Dynamic state base address */
- OUT_BATCH(1); /* Indirect object base address */
- OUT_BATCH(1); /* Instruction base address */
+ /* General state base address: stateless DP read/write requests */
+ OUT_BATCH(1);
+ /* Surface state base address:
+ * BINDING_TABLE_STATE
+ * SURFACE_STATE
+ */
+ OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
+ /* Dynamic state base address:
+ * SAMPLER_STATE
+ * SAMPLER_BORDER_COLOR_STATE
+ * CLIP, SF, WM/CC viewport state
+ * COLOR_CALC_STATE
+ * DEPTH_STENCIL_STATE
+ * BLEND_STATE
+ * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
+ * Disable is clear, which we rely on)
+ */
+ OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
+ I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
+
+ OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
+ OUT_BATCH(1); /* Instruction base address: shader kernels (incl. SIP) */
OUT_BATCH(1); /* General state upper bound */
OUT_BATCH(1); /* Dynamic state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(intel->batch->buf, I915_GEM_DOMAIN_SAMPLER, 0,
+ OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* Instruction base address */
BEGIN_BATCH(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(intel->batch->buf, I915_GEM_DOMAIN_SAMPLER, 0,
+ OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* General state upper bound */
projects / mesa.git / blobdiff