#include "intel_batchbuffer.h"
#include "intel_fbo.h"
#include "intel_mipmap_tree.h"
-#include "intel_regions.h"
#include "brw_context.h"
#include "brw_state.h"
{
struct gl_context *ctx = &brw->ctx;
- /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined. */
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0); /* xmin, ymin */
.dirty = {
.mesa = _NEW_BUFFERS,
.brw = BRW_NEW_CONTEXT,
- .cache = 0
},
.emit = upload_drawing_rect
};
const struct brw_tracked_state brw_psp_urb_cbs = {
.dirty = {
.mesa = 0,
- .brw = (BRW_NEW_URB_FENCE |
- BRW_NEW_BATCH |
- BRW_NEW_STATE_BASE_ADDRESS),
- .cache = (CACHE_NEW_VS_UNIT |
- CACHE_NEW_FF_GS_UNIT |
- CACHE_NEW_FF_GS_PROG |
- CACHE_NEW_CLIP_UNIT |
- CACHE_NEW_SF_UNIT |
- CACHE_NEW_WM_UNIT |
- CACHE_NEW_CC_UNIT)
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_FF_GS_PROG_DATA |
+ BRW_NEW_GEN4_UNIT_STATE |
+ BRW_NEW_STATE_BASE_ADDRESS |
+ BRW_NEW_URB_FENCE,
},
.emit = upload_psp_urb_cbs,
};
uint32_t tile_mask_x = 0, tile_mask_y = 0;
if (depth_mt) {
- intel_region_get_tile_masks(depth_mt->region,
- &tile_mask_x, &tile_mask_y, false);
+ intel_miptree_get_tile_masks(depth_mt, &tile_mask_x, &tile_mask_y, false);
- if (intel_miptree_slice_has_hiz(depth_mt, depth_level, depth_layer)) {
+ if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
- intel_region_get_tile_masks(depth_mt->hiz_mt->region,
- &hiz_tile_mask_x, &hiz_tile_mask_y, false);
+ intel_miptree_get_tile_masks(depth_mt->hiz_buf->mt,
+ &hiz_tile_mask_x, &hiz_tile_mask_y,
+ false);
/* Each HiZ row represents 2 rows of pixels */
hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1;
tile_mask_y |= 63;
} else {
uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
- intel_region_get_tile_masks(stencil_mt->region,
- &stencil_tile_mask_x,
- &stencil_tile_mask_y, false);
+ intel_miptree_get_tile_masks(stencil_mt,
+ &stencil_tile_mask_x,
+ &stencil_tile_mask_y, false);
tile_mask_x |= stencil_tile_mask_x;
tile_mask_y |= stencil_tile_mask_y;
if (stencil_irb)
brw->depthstencil.stencil_mt = get_stencil_miptree(stencil_irb);
- /* Gen7+ doesn't require the workarounds, since we always program the
+ /* Gen6+ doesn't require the workarounds, since we always program the
* surface state at the start of the whole surface.
*/
- if (brw->gen >= 7)
+ if (brw->gen >= 6)
return;
/* Check if depth buffer is in depth/stencil format. If so, then it's only
depth_mt = depth_irb->mt;
brw->depthstencil.depth_mt = depth_mt;
brw->depthstencil.depth_offset =
- intel_region_get_aligned_offset(depth_mt->region,
- depth_irb->draw_x & ~tile_mask_x,
- depth_irb->draw_y & ~tile_mask_y,
- false);
+ intel_miptree_get_aligned_offset(depth_mt,
+ depth_irb->draw_x & ~tile_mask_x,
+ depth_irb->draw_y & ~tile_mask_y,
+ false);
if (intel_renderbuffer_has_hiz(depth_irb)) {
brw->depthstencil.hiz_offset =
- intel_region_get_aligned_offset(depth_mt->region,
- depth_irb->draw_x & ~tile_mask_x,
- (depth_irb->draw_y & ~tile_mask_y) /
- 2,
- false);
+ intel_miptree_get_aligned_offset(depth_mt,
+ depth_irb->draw_x & ~tile_mask_x,
+ (depth_irb->draw_y & ~tile_mask_y) / 2,
+ false);
}
}
if (stencil_irb) {
* that the region is untiled even though it's W tiled.
*/
brw->depthstencil.stencil_offset =
- (stencil_draw_y & ~tile_mask_y) * stencil_mt->region->pitch +
+ (stencil_draw_y & ~tile_mask_y) * stencil_mt->pitch +
(stencil_draw_x & ~tile_mask_x) * 64;
}
}
/* Prior to Gen7, if using separate stencil, hiz must be enabled. */
assert(brw->gen >= 7 || !separate_stencil || hiz);
- assert(brw->gen < 6 || depth_mt->region->tiling == I915_TILING_Y);
- assert(!hiz || depth_mt->region->tiling == I915_TILING_Y);
+ assert(brw->gen < 6 || depth_mt->tiling == I915_TILING_Y);
+ assert(!hiz || depth_mt->tiling == I915_TILING_Y);
depthbuffer_format = brw_depthbuffer_format(brw);
depth_surface_type = BRW_SURFACE_2D;
}
if (depth_mt)
- brw_render_cache_set_check_flush(brw, depth_mt->region->bo);
+ brw_render_cache_set_check_flush(brw, depth_mt->bo);
if (stencil_mt)
- brw_render_cache_set_check_flush(brw, stencil_mt->region->bo);
+ brw_render_cache_set_check_flush(brw, stencil_mt->bo);
brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
depthbuffer_format, depth_surface_type,
* non-pipelined state that will need the PIPE_CONTROL workaround.
*/
if (brw->gen == 6) {
- intel_emit_post_sync_nonzero_flush(brw);
intel_emit_depth_stall_flushes(brw);
}
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
- OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) |
+ OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
(depthbuffer_format << 18) |
((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
(BRW_TILEWALK_YMAJOR << 26) |
- ((depth_mt ? depth_mt->region->tiling != I915_TILING_NONE : 1)
+ ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1)
<< 27) |
(depth_surface_type << 29));
if (depth_mt) {
- OUT_RELOC(depth_mt->region->bo,
+ OUT_RELOC(depth_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
depth_offset);
} else {
/* Emit hiz buffer. */
if (hiz) {
- struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
+ struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
- OUT_BATCH(hiz_mt->region->pitch - 1);
- OUT_RELOC(hiz_mt->region->bo,
+ OUT_BATCH(hiz_mt->pitch - 1);
+ OUT_RELOC(hiz_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
brw->depthstencil.hiz_offset);
ADVANCE_BATCH();
/* Emit stencil buffer. */
if (separate_stencil) {
- struct intel_region *region = stencil_mt->region;
-
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
/* The stencil buffer has quirky pitch requirements. From Vol 2a,
* The pitch must be set to 2x the value computed based on width, as
* the stencil buffer is stored with two rows interleaved.
*/
- OUT_BATCH(2 * region->pitch - 1);
- OUT_RELOC(region->bo,
+ OUT_BATCH(2 * stencil_mt->pitch - 1);
+ OUT_RELOC(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
brw->depthstencil.stencil_offset);
ADVANCE_BATCH();
* when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
*/
if (brw->gen >= 6 || hiz) {
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
GEN5_DEPTH_CLEAR_VALID |
.dirty = {
.mesa = _NEW_BUFFERS,
.brw = BRW_NEW_BATCH,
- .cache = 0,
},
.emit = brw_emit_depthbuffer,
};
if (!ctx->Polygon.StippleFlag)
return;
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
BEGIN_BATCH(33);
OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
const struct brw_tracked_state brw_polygon_stipple = {
.dirty = {
- .mesa = (_NEW_POLYGONSTIPPLE |
- _NEW_POLYGON),
+ .mesa = _NEW_POLYGON |
+ _NEW_POLYGONSTIPPLE,
.brw = BRW_NEW_CONTEXT,
- .cache = 0
},
.emit = upload_polygon_stipple
};
if (!ctx->Polygon.StippleFlag)
return;
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
const struct brw_tracked_state brw_polygon_stipple_offset = {
.dirty = {
- .mesa = (_NEW_BUFFERS |
- _NEW_POLYGON),
+ .mesa = _NEW_BUFFERS |
+ _NEW_POLYGON,
.brw = BRW_NEW_CONTEXT,
- .cache = 0
},
.emit = upload_polygon_stipple_offset
};
if (brw->gen == 4 && !brw->is_g4x)
return;
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
/* use legacy aa line coverage computation */
.dirty = {
.mesa = _NEW_LINE,
.brw = BRW_NEW_CONTEXT,
- .cache = 0
},
.emit = upload_aa_line_parameters
};
if (!ctx->Line.StippleFlag)
return;
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
OUT_BATCH(ctx->Line.StipplePattern);
.dirty = {
.mesa = _NEW_LINE,
.brw = BRW_NEW_CONTEXT,
- .cache = 0
},
.emit = upload_line_stipple
};
{
const bool is_965 = brw->gen == 4 && !brw->is_g4x;
- /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
/* Select the 3D pipeline (as opposed to media) */
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
BEGIN_BATCH(1);
- OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | 0);
+ OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | (brw->gen >= 9 ? (3 << 8) : 0));
ADVANCE_BATCH();
if (brw->gen < 6) {
const uint32_t _3DSTATE_VF_STATISTICS =
is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS;
BEGIN_BATCH(1);
- OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 |
- (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
+ OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 | 1);
ADVANCE_BATCH();
}
.dirty = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT,
- .cache = 0
},
.emit = brw_upload_invariant_state
};
if (brw->gen >= 6) {
uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
- if (brw->gen == 6)
- intel_emit_post_sync_nonzero_flush(brw);
-
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
OUT_BATCH(mocs << 8 | /* General State Memory Object Control State */
const struct brw_tracked_state brw_state_base_address = {
.dirty = {
.mesa = 0,
- .brw = (BRW_NEW_BATCH |
- BRW_NEW_PROGRAM_CACHE),
- .cache = 0,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_PROGRAM_CACHE,
},
.emit = upload_state_base_address
};
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