Merge remote-tracking branch 'mesa-public/master' into vulkan

[mesa.git] / src / mesa / drivers / dri / i965 / brw_nir.c

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
index 11f111382f45c846e81ae1ba3ddebf0244a1bcbd..8c1a34ee17a35a1e72bbf9c8903225678bf75a53 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -189,10 +189,6 @@ brw_create_nir(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    const nir_shader_compiler_options *options =
       ctx->Const.ShaderCompilerOptions[stage].NirOptions;
-   static const nir_lower_tex_options tex_options = {
-      .lower_txp = ~0,
-   };
-   bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
    nir_shader *nir;
 
    /* First, lower the GLSL IR or Mesa IR to NIR */
@@ -204,7 +200,39 @@ brw_create_nir(struct brw_context *brw,
    }
    nir_validate_shader(nir);
 
-   if (stage == MESA_SHADER_GEOMETRY) {
+   brw_preprocess_nir(nir, brw->intelScreen->devinfo, is_scalar);
+
+   if (shader_prog) {
+      nir_lower_samplers(nir, shader_prog);
+      nir_validate_shader(nir);
+
+      nir_lower_atomics(nir, shader_prog);
+      nir_validate_shader(nir);
+   }
+
+   brw_postprocess_nir(nir, brw->intelScreen->devinfo, is_scalar);
+
+   static GLuint msg_id = 0;
+   _mesa_gl_debug(&brw->ctx, &msg_id,
+                  MESA_DEBUG_SOURCE_SHADER_COMPILER,
+                  MESA_DEBUG_TYPE_OTHER,
+                  MESA_DEBUG_SEVERITY_NOTIFICATION,
+                  "%s NIR shader:\n",
+                  _mesa_shader_stage_to_abbrev(nir->stage));
+
+   return nir;
+}
+
+void
+brw_preprocess_nir(nir_shader *nir,
+                   const struct brw_device_info *devinfo,
+                   bool is_scalar)
+{
+   static const nir_lower_tex_options tex_options = {
+      .lower_txp = ~0,
+   };
+
+   if (nir->stage == MESA_SHADER_GEOMETRY) {
       nir_lower_gs_intrinsics(nir);
       nir_validate_shader(nir);
    }
@@ -229,6 +257,15 @@ brw_create_nir(struct brw_context *brw,
 
    /* Get rid of split copies */
    nir_optimize(nir, is_scalar);
+}
+
+void
+brw_postprocess_nir(nir_shader *nir,
+                    const struct brw_device_info *devinfo,
+                    bool is_scalar)
+{
+   bool debug_enabled =
+      (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage));
 
    brw_nir_lower_inputs(nir, is_scalar);
    brw_nir_lower_outputs(nir, is_scalar);
@@ -241,22 +278,12 @@ brw_create_nir(struct brw_context *brw,
    nir_remove_dead_variables(nir);
    nir_validate_shader(nir);
 
-   if (shader_prog) {
-      nir_lower_samplers(nir, shader_prog);
-      nir_validate_shader(nir);
-   }
-
    nir_lower_system_values(nir);
    nir_validate_shader(nir);
 
-   if (shader_prog) {
-      nir_lower_atomics(nir, shader_prog);
-      nir_validate_shader(nir);
-   }
-
    nir_optimize(nir, is_scalar);
 
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       /* Try and fuse multiply-adds */
       nir_opt_peephole_ffma(nir);
       nir_validate_shader(nir);
@@ -283,7 +310,7 @@ brw_create_nir(struct brw_context *brw,
       }
 
       fprintf(stderr, "NIR (SSA form) for %s shader:\n",
-              _mesa_shader_stage_to_string(stage));
+              _mesa_shader_stage_to_string(nir->stage));
       nir_print_shader(nir, stderr);
    }
 
@@ -303,18 +330,16 @@ brw_create_nir(struct brw_context *brw,
     * run it last because it stashes data in instr->pass_flags and we don't
     * want that to be squashed by other NIR passes.
     */
-   if (brw->gen <= 5)
+   if (devinfo->gen <= 5)
       brw_nir_analyze_boolean_resolves(nir);
 
    nir_sweep(nir);
 
    if (unlikely(debug_enabled)) {
       fprintf(stderr, "NIR (final form) for %s shader:\n",
-              _mesa_shader_stage_to_string(stage));
+              _mesa_shader_stage_to_string(nir->stage));
       nir_print_shader(nir, stderr);
    }
-
-   return nir;
 }
 
 enum brw_reg_type