nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes

[mesa.git] / src / mesa / drivers / dri / i965 / brw_nir.h

diff --git a/src/mesa/drivers/dri/i965/brw_nir.h b/src/mesa/drivers/dri/i965/brw_nir.h
index 618531096539971a03cd8d95c6068013f11fcfbf..ecb4118980605f37e257ae95b90be983b3405c61 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_nir.h
+++ b/src/mesa/drivers/dri/i965/brw_nir.h
@@ -23,15 +23,18 @@
 
 #pragma once
 
-#include "brw_context.h"
 #include "brw_reg.h"
-#include "brw_shader.h"
 #include "compiler/nir/nir.h"
+#include "brw_compiler.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+int type_size_scalar(const struct glsl_type *type);
+int type_size_vec4(const struct glsl_type *type);
+int type_size_dvec4(const struct glsl_type *type);
+
 static inline int
 type_size_scalar_bytes(const struct glsl_type *type)
 {
@@ -94,21 +97,24 @@ nir_shader *brw_preprocess_nir(const struct brw_compiler *compiler,
 bool brw_nir_lower_intrinsics(nir_shader *nir,
                               struct brw_stage_prog_data *prog_data);
 void brw_nir_lower_vs_inputs(nir_shader *nir,
-                             const struct brw_device_info *devinfo,
                              bool is_scalar,
                              bool use_legacy_snorm_formula,
                              const uint8_t *vs_attrib_wa_flags);
 void brw_nir_lower_vue_inputs(nir_shader *nir, bool is_scalar,
                               const struct brw_vue_map *vue_map);
 void brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue);
-void brw_nir_lower_fs_inputs(nir_shader *nir);
+void brw_nir_lower_fs_inputs(nir_shader *nir, struct brw_vue_map *vue_map,
+                             struct gl_program *prog,
+                             const struct gen_device_info *devinfo,
+                             const struct brw_wm_prog_key *key);
 void brw_nir_lower_vue_outputs(nir_shader *nir, bool is_scalar);
-void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue);
+void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue,
+                               GLenum tes_primitive_mode);
 void brw_nir_lower_fs_outputs(nir_shader *nir);
 void brw_nir_lower_cs_shared(nir_shader *nir);
 
 nir_shader *brw_postprocess_nir(nir_shader *nir,
-                                const struct brw_device_info *devinfo,
+                                const struct brw_compiler *compiler,
                                 bool is_scalar);
 
 bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
@@ -120,7 +126,7 @@ bool brw_nir_apply_trig_workarounds(nir_shader *nir);
 void brw_nir_apply_tcs_quads_workaround(nir_shader *nir);
 
 nir_shader *brw_nir_apply_sampler_key(nir_shader *nir,
-                                      const struct brw_device_info *devinfo,
+                                      const struct brw_compiler *compiler,
                                       const struct brw_sampler_prog_key_data *key,
                                       bool is_scalar);
 
@@ -129,7 +135,6 @@ enum brw_reg_type brw_type_for_nir_type(nir_alu_type type);
 enum glsl_base_type brw_glsl_base_type_for_nir_type(nir_alu_type type);
 
 void brw_nir_setup_glsl_uniforms(nir_shader *shader,
-                                 struct gl_shader_program *shader_prog,
                                  const struct gl_program *prog,
                                  struct brw_stage_prog_data *stage_prog_data,
                                  bool is_scalar);
@@ -139,6 +144,11 @@ void brw_nir_setup_arb_uniforms(nir_shader *shader, struct gl_program *prog,
 
 bool brw_nir_opt_peephole_ffma(nir_shader *shader);
 
+#define BRW_NIR_FRAG_OUTPUT_INDEX_SHIFT 0
+#define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
+#define BRW_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1
+#define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
+
 #ifdef __cplusplus
 }
 #endif