i965/urb: fixes division by zero

[mesa.git] / src / mesa / drivers / dri / i965 / brw_pipe_control.c

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 6c636d261392f551fb5352382141608f169c62dc..4672efdffc37323f3a9a948f59a7fa10366b2e7e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -51,7 +51,7 @@ gen8_add_cs_stall_workaround_bits(uint32_t *flags)
                       PIPE_CONTROL_WRITE_TIMESTAMP |
                       PIPE_CONTROL_STALL_AT_SCOREBOARD |
                       PIPE_CONTROL_DEPTH_STALL |
-                      PIPE_CONTROL_DATA_CACHE_INVALIDATE;
+                      PIPE_CONTROL_DATA_CACHE_FLUSH;
 
    /* If we're doing a CS stall, and don't already have one of the
     * workaround bits set, add "Stall at Pixel Scoreboard."
@@ -338,8 +338,6 @@ brw_emit_mi_flush(struct brw_context *brw)
       }
       brw_emit_pipe_control_flush(brw, flags);
    }
-
-   brw_render_cache_set_clear(brw);
 }
 
 int