i965/skl: Send a message header when doing constant loads SIMD4x2

[mesa.git] / src / mesa / drivers / dri / i965 / brw_program.c

diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index e56ece0b3a8ac82b1685e68941e0f40becc6573a..70b5a6289e22b50cd07c4dcc76ddac3b9ea1c4c5 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -42,7 +42,9 @@
 #include "glsl/ir.h"
 
 #include "brw_context.h"
+#include "brw_shader.h"
 #include "brw_wm.h"
+#include "intel_batchbuffer.h"
 
 static unsigned
 get_new_program_id(struct intel_screen *screen)
@@ -119,14 +121,6 @@ static void brwDeleteProgram( struct gl_context *ctx,
 }
 
 
-static GLboolean
-brwIsProgramNative(struct gl_context *ctx,
-                  GLenum target,
-                  struct gl_program *prog)
-{
-   return true;
-}
-
 static GLboolean
 brwProgramStringNotify(struct gl_context *ctx,
                       GLenum target,
@@ -144,6 +138,10 @@ brwProgramStringNotify(struct gl_context *ctx,
       if (newFP == curFP)
         brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
       newFP->id = get_new_program_id(brw->intelScreen);
+
+      brw_add_texrect_params(prog);
+
+      brw_fs_precompile(ctx, NULL, prog);
       break;
    }
    case GL_VERTEX_PROGRAM_ARB: {
@@ -162,6 +160,10 @@ brwProgramStringNotify(struct gl_context *ctx,
       /* Also tell tnl about it:
        */
       _tnl_program_string(ctx, target, prog);
+
+      brw_add_texrect_params(prog);
+
+      brw_vs_precompile(ctx, NULL, prog);
       break;
    }
    default:
@@ -175,11 +177,46 @@ brwProgramStringNotify(struct gl_context *ctx,
       unreachable("Unexpected target in brwProgramStringNotify");
    }
 
-   brw_add_texrect_params(prog);
-
    return true;
 }
 
+static void
+brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
+{
+   struct brw_context *brw = brw_context(ctx);
+   unsigned bits = (PIPE_CONTROL_DATA_CACHE_INVALIDATE |
+                    PIPE_CONTROL_NO_WRITE |
+                    PIPE_CONTROL_CS_STALL);
+   assert(brw->gen >= 7 && brw->gen <= 8);
+
+   if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
+                   GL_ELEMENT_ARRAY_BARRIER_BIT |
+                   GL_COMMAND_BARRIER_BIT))
+      bits |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+
+   if (barriers & GL_UNIFORM_BARRIER_BIT)
+      bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
+               PIPE_CONTROL_CONST_CACHE_INVALIDATE);
+
+   if (barriers & GL_TEXTURE_FETCH_BARRIER_BIT)
+      bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+
+   if (barriers & GL_TEXTURE_UPDATE_BARRIER_BIT)
+      bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
+
+   if (barriers & GL_FRAMEBUFFER_BARRIER_BIT)
+      bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+               PIPE_CONTROL_RENDER_TARGET_FLUSH);
+
+   /* Typed surface messages are handled by the render cache on IVB, so we
+    * need to flush it too.
+    */
+   if (brw->gen == 7 && !brw->is_haswell)
+      bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
+
+   brw_emit_pipe_control_flush(brw, bits);
+}
+
 void
 brw_add_texrect_params(struct gl_program *prog)
 {
@@ -233,11 +270,12 @@ void brwInitFragProgFuncs( struct dd_function_table *functions )
 
    functions->NewProgram = brwNewProgram;
    functions->DeleteProgram = brwDeleteProgram;
-   functions->IsProgramNative = brwIsProgramNative;
    functions->ProgramStringNotify = brwProgramStringNotify;
 
    functions->NewShader = brw_new_shader;
    functions->LinkShader = brw_link_shader;
+
+   functions->MemoryBarrier = brw_memory_barrier;
 }
 
 void
@@ -564,8 +602,7 @@ brw_stage_prog_data_free(const void *p)
 }
 
 void
-brw_dump_ir(struct brw_context *brw, const char *stage,
-            struct gl_shader_program *shader_prog,
+brw_dump_ir(const char *stage, struct gl_shader_program *shader_prog,
             struct gl_shader *shader, struct gl_program *prog)
 {
    if (shader_prog) {