Added few more stubs so that control reaches to DestroyDevice().

[mesa.git] / src / mesa / drivers / dri / i965 / brw_program.c

diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 8d1d576b87d28a99e4933961a198421e095338bf..b3db2cc61bbd8af91e98694f6cc4256c6ac09b51 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -30,7 +30,6 @@
   */
 
 #include <pthread.h>
-#include "main/imports.h"
 #include "main/glspirv.h"
 #include "program/prog_parameter.h"
 #include "program/prog_print.h"
@@ -63,17 +62,18 @@ static bool
 brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
 {
    if (is_scalar) {
-      nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
+      nir_assign_var_locations(nir, nir_var_uniform, &nir->num_uniforms,
                                type_size_scalar_bytes);
       return nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes, 0);
    } else {
-      nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
+      nir_assign_var_locations(nir, nir_var_uniform, &nir->num_uniforms,
                                type_size_vec4_bytes);
       return nir_lower_io(nir, nir_var_uniform, type_size_vec4_bytes, 0);
    }
 }
 
-static struct gl_program *brwNewProgram(struct gl_context *ctx, GLenum target,
+static struct gl_program *brwNewProgram(struct gl_context *ctx,
+                                        gl_shader_stage stage,
                                         GLuint id, bool is_arb_asm);
 
 nir_shader *
@@ -95,10 +95,19 @@ brw_create_nir(struct brw_context *brw,
          nir = _mesa_spirv_to_nir(ctx, shader_prog, stage, options);
       } else {
          nir = glsl_to_nir(ctx, shader_prog, stage, options);
+
+         /* Remap the locations to slots so those requiring two slots will
+          * occupy two locations. For instance, if we have in the IR code a
+          * dvec3 attr0 in location 0 and vec4 attr1 in location 1, in NIR attr0
+          * will use locations/slots 0 and 1, and attr1 will use location/slot 2
+          */
+         if (nir->info.stage == MESA_SHADER_VERTEX)
+            nir_remap_dual_slot_attributes(nir, &prog->DualSlotInputs);
       }
       assert (nir);
 
-      nir_remove_dead_variables(nir, nir_var_shader_in | nir_var_shader_out);
+      nir_remove_dead_variables(nir, nir_var_shader_in | nir_var_shader_out,
+                                NULL);
       nir_validate_shader(nir, "after glsl_to_nir or spirv_to_nir");
       NIR_PASS_V(nir, nir_lower_io_to_temporaries,
                  nir_shader_get_entrypoint(nir), true, false);
@@ -152,8 +161,6 @@ brw_create_nir(struct brw_context *brw,
       }
    }
 
-   NIR_PASS_V(nir, brw_nir_lower_uniforms, is_scalar);
-
    return nir;
 }
 
@@ -174,11 +181,12 @@ brw_nir_lower_resources(nir_shader *nir, struct gl_shader_program *shader_prog,
                         struct gl_program *prog,
                         const struct gen_device_info *devinfo)
 {
+   NIR_PASS_V(nir, brw_nir_lower_uniforms, nir->options->lower_to_scalar);
    NIR_PASS_V(prog->nir, gl_nir_lower_samplers, shader_prog);
    prog->info.textures_used = prog->nir->info.textures_used;
    prog->info.textures_used_by_txf = prog->nir->info.textures_used_by_txf;
 
-   NIR_PASS_V(prog->nir, brw_nir_lower_image_load_store, devinfo);
+   NIR_PASS_V(prog->nir, brw_nir_lower_image_load_store, devinfo, NULL);
 
    if (prog->nir->info.stage == MESA_SHADER_COMPUTE &&
        shader_prog->data->spirv) {
@@ -212,7 +220,8 @@ get_new_program_id(struct intel_screen *screen)
    return p_atomic_inc_return(&screen->program_id);
 }
 
-static struct gl_program *brwNewProgram(struct gl_context *ctx, GLenum target,
+static struct gl_program *brwNewProgram(struct gl_context *ctx,
+                                        gl_shader_stage stage,
                                         GLuint id, bool is_arb_asm)
 {
    struct brw_context *brw = brw_context(ctx);
@@ -221,7 +230,7 @@ static struct gl_program *brwNewProgram(struct gl_context *ctx, GLenum target,
    if (prog) {
       prog->id = get_new_program_id(brw->screen);
 
-      return _mesa_init_gl_program(&prog->program, target, id, is_arb_asm);
+      return _mesa_init_gl_program(&prog->program, stage, id, is_arb_asm);
    }
 
    return NULL;
@@ -459,12 +468,29 @@ brw_alloc_stage_scratch(struct brw_context *brw,
        * brw->screen->subslice_total is the TOTAL number of subslices
        * and we wish to view that there are 4 subslices per slice
        * instead of the actual number of subslices per slice.
+       *
+       * For, ICL, scratch space allocation is based on the number of threads
+       * in the base configuration.
        */
-      if (devinfo->gen >= 9 && devinfo->gen < 11)
+      if (devinfo->gen == 11)
+         subslices = 8;
+      else if (devinfo->gen >= 9 && devinfo->gen < 11)
          subslices = 4 * brw->screen->devinfo.num_slices;
 
       unsigned scratch_ids_per_subslice;
-      if (devinfo->is_haswell) {
+      if (devinfo->gen >= 11) {
+         /* The MEDIA_VFE_STATE docs say:
+          *
+          *    "Starting with this configuration, the Maximum Number of
+          *     Threads must be set to (#EU * 8) for GPGPU dispatches.
+          *
+          *     Although there are only 7 threads per EU in the configuration,
+          *     the FFTID is calculated as if there are 8 threads per EU,
+          *     which in turn requires a larger amount of Scratch Space to be
+          *     allocated by the driver."
+          */
+         scratch_ids_per_subslice = 8 * 8;
+      } else if (devinfo->is_haswell) {
          /* WaCSScratchSize:hsw
           *
           * Haswell's scratch space address calculation appears to be sparse