{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
- return (double)gpu_timestamp * devinfo->timebase_scale;
+ return (1000000000ull * gpu_timestamp) / devinfo->timestamp_frequency;
}
/* As best we know currently, the Gen HW timestamps are 36bits across
flags |= PIPE_CONTROL_CS_STALL;
brw_emit_pipe_control_write(brw, flags,
- query_bo, idx * sizeof(uint64_t), 0, 0);
+ query_bo, idx * sizeof(uint64_t), 0);
}
/**
if (brw->gen == 9 && brw->gt == 4)
flags |= PIPE_CONTROL_CS_STALL;
+ if (brw->gen >= 10) {
+ /* "Driver must program PIPE_CONTROL with only Depth Stall Enable bit set
+ * prior to programming a PIPE_CONTROL with Write PS Depth Count Post sync
+ * operation."
+ */
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
+ }
+
brw_emit_pipe_control_write(brw, flags,
- query_bo, idx * sizeof(uint64_t),
- 0, 0);
+ query_bo, idx * sizeof(uint64_t), 0);
}
/**
}
}
- results = brw_bo_map_cpu(brw, query->bo, MAP_READ);
+ results = brw_bo_map(brw, query->bo, MAP_READ);
switch (query->Base.Target) {
case GL_TIME_ELAPSED_EXT:
/* The query BO contains the starting and ending timestamps.