i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_sf.h

diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h
index 971f5fb0a245522d6f387a2b9c3fcc3845732f48..15102ac6119fb9926ddcac9ac8bd7396611562c4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sf.h
+++ b/src/mesa/drivers/dri/i965/brw_sf.h
@@ -58,7 +58,7 @@ struct brw_sf_prog_key {
 };
 
 struct brw_sf_compile {
-   struct brw_compile func;
+   struct brw_codegen func;
    struct brw_sf_prog_key key;
    struct brw_sf_prog_data prog_data;
 
@@ -94,6 +94,9 @@ struct brw_sf_compile {
    GLuint nr_setup_regs;
    int urb_entry_read_offset;
 
+   /** The last known value of the f0.0 flag register. */
+   unsigned flag_value;
+
    struct brw_vue_map vue_map;
    bool has_flat_shading;
 };