#include "brw_state.h"
#include "brw_defines.h"
#include "main/macros.h"
-#include "intel_fbo.h"
static void upload_sf_vp(struct brw_context *brw)
{
* for DrawBuffer->_[XY]{min,max}
*/
- /* The scissor only needs to handle the intersection of drawable and
- * scissor rect. Clipping to the boundaries of static shared buffers
- * for front/back/depth is covered by looping over cliprects in brw_draw.c.
+ /* The scissor only needs to handle the intersection of drawable
+ * and scissor rect, since there are no longer cliprects for shared
+ * buffers with DRI2.
*
* Note that the hardware's coordinates are inclusive, while Mesa's min is
* inclusive but max is exclusive.
*/
- if (render_to_fbo) {
+
+ if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
+ ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
+ /* If the scissor was out of bounds and got clamped to 0
+ * width/height at the bounds, the subtraction of 1 from
+ * maximums could produce a negative number and thus not clip
+ * anything. Instead, just provide a min > max scissor inside
+ * the bounds, which produces the expected no rendering.
+ */
+ sfv.scissor.xmin = 1;
+ sfv.scissor.xmax = 0;
+ sfv.scissor.ymin = 1;
+ sfv.scissor.ymax = 0;
+ } else if (render_to_fbo) {
/* texmemory: Y=0=bottom */
sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
}
dri_bo_unreference(brw->sf.vp_bo);
- brw->sf.vp_bo = brw_cache_data( &brw->cache, BRW_SF_VP, &sfv, NULL, 0 );
+ brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP, &sfv, sizeof(sfv),
+ NULL, 0);
}
const struct brw_tracked_state brw_sf_vp = {
sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
dri_bo **reloc_bufs)
{
+ struct intel_context *intel = &brw->intel;
struct brw_sf_unit_state sf;
dri_bo *bo;
int chipset_max_threads;
sf.thread3.dispatch_grf_start_reg = 3;
- if (BRW_IS_IGDNG(brw))
+ if (intel->gen == 5)
sf.thread3.urb_entry_read_offset = 3;
else
sf.thread3.urb_entry_read_offset = 1;
sf.thread4.nr_urb_entries = key->nr_urb_entries;
sf.thread4.urb_entry_allocation_size = key->sfsize - 1;
- /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or
- * 48(IGDNG) threads
+ /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
+ * 48 (Ironlake) threads.
*/
- if (BRW_IS_IGDNG(brw))
+ if (intel->gen == 5)
chipset_max_threads = 48;
else
chipset_max_threads = 24;
bo = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
key, sizeof(*key),
reloc_bufs, 2,
- &sf, sizeof(sf),
- NULL, NULL);
+ &sf, sizeof(sf));
/* STATE_PREFETCH command description describes this state as being
* something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.