#include "brw_state.h"
#include "brw_defines.h"
#include "main/macros.h"
+#include "brw_sf.h"
static void upload_sf_vp(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &intel->ctx;
const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
struct brw_sf_viewport *sfv;
GLfloat y_scale, y_bias;
- const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
+ const bool render_to_fbo = (ctx->DrawBuffer->Name != 0);
const GLfloat *v = ctx->Viewport._WindowMap.m;
- sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
+ sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
+ sizeof(*sfv), 32, &brw->sf.vp_offset);
memset(sfv, 0, sizeof(*sfv));
if (render_to_fbo) {
.brw = BRW_NEW_BATCH,
.cache = 0
},
- .prepare = upload_sf_vp
+ .emit = upload_sf_vp
};
+/**
+ * Compute the offset within the URB (expressed in 256-bit register
+ * increments) that should be used to read the VUE in th efragment shader.
+ */
+int
+brw_sf_compute_urb_entry_read_offset(struct intel_context *intel)
+{
+ if (intel->gen == 5)
+ return 3;
+ else
+ return 1;
+}
+
static void upload_sf_unit( struct brw_context *brw )
{
struct intel_context *intel = &brw->intel;
int chipset_max_threads;
bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
- sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
+ sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
+ sizeof(*sf), 64, &brw->sf.state_offset);
memset(sf, 0, sizeof(*sf));
- /* CACHE_NEW_SF_PROG */
+ /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_SF_PROG */
sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
- sf->thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
+ sf->thread0.kernel_start_pointer =
+ brw_program_reloc(brw,
+ brw->sf.state_offset +
+ offsetof(struct brw_sf_unit_state, thread0),
+ brw->sf.prog_offset +
+ (sf->thread0.grf_reg_count << 1)) >> 6;
sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
sf->thread3.dispatch_grf_start_reg = 3;
- if (intel->gen == 5)
- sf->thread3.urb_entry_read_offset = 3;
- else
- sf->thread3.urb_entry_read_offset = 1;
+ sf->thread3.urb_entry_read_offset =
+ brw_sf_compute_urb_entry_read_offset(intel);
/* CACHE_NEW_SF_PROG */
sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
sf->thread4.max_threads = MIN2(chipset_max_threads,
brw->urb.nr_sf_entries) - 1;
- if (unlikely(INTEL_DEBUG & DEBUG_SINGLE_THREAD))
- sf->thread4.max_threads = 0;
-
if (unlikely(INTEL_DEBUG & DEBUG_STATS))
sf->thread4.stats_enable = 1;
/* STATE_PREFETCH command description describes this state as being
* something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
*/
- /* Emit SF program relocation */
- drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
- offsetof(struct brw_sf_unit_state, thread0)),
- brw->sf.prog_bo, sf->thread0.grf_reg_count << 1,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
/* Emit SF viewport relocation */
drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
_NEW_SCISSOR |
_NEW_BUFFERS),
.brw = (BRW_NEW_BATCH |
+ BRW_NEW_PROGRAM_CACHE |
BRW_NEW_URB_FENCE),
.cache = (CACHE_NEW_SF_VP |
CACHE_NEW_SF_PROG)
},
- .prepare = upload_sf_unit,
+ .emit = upload_sf_unit,
};