i965/vec4: Make with_writemask() non-static.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 6515e28cf57f28506cf72b8d7a7e8001bd8c5ce8..4bed5503ff11a5da0cee3ccef16b51f3bce1dbc9 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -41,8 +41,7 @@
 
 static void upload_sf_vp(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
    struct brw_sf_viewport *sfv;
    GLfloat y_scale, y_bias;
@@ -126,12 +125,11 @@ const struct brw_tracked_state brw_sf_vp = {
 
 static void upload_sf_unit( struct brw_context *brw )
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    struct brw_sf_unit_state *sf;
    drm_intel_bo *bo = brw->batch.bo;
    int chipset_max_threads;
-   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
+   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
 
    sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
                        sizeof(*sf), 64, &brw->sf.state_offset);
@@ -162,7 +160,7 @@ static void upload_sf_unit( struct brw_context *brw )
    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
     * 48 (Ironlake) threads.
     */
-   if (intel->gen == 5)
+   if (brw->gen == 5)
       chipset_max_threads = 48;
    else
       chipset_max_threads = 24;