+#include "main/mtypes.h"
+#include "main/macros.h"
+#include "main/fbobject.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
-#include "main/macros.h"
#include "brw_sf.h"
static void upload_sf_vp(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
struct brw_sf_viewport *sfv;
GLfloat y_scale, y_bias;
- const bool render_to_fbo = (ctx->DrawBuffer->Name != 0);
+ const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
const GLfloat *v = ctx->Viewport._WindowMap.m;
sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
.emit = upload_sf_vp
};
-/**
- * Compute the offset within the URB (expressed in 256-bit register
- * increments) that should be used to read the VUE in th efragment shader.
- */
-int
-brw_sf_compute_urb_entry_read_offset(struct intel_context *intel)
-{
- if (intel->gen == 5)
- return 3;
- else
- return 1;
-}
-
static void upload_sf_unit( struct brw_context *brw )
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
struct brw_sf_unit_state *sf;
- drm_intel_bo *bo = intel->batch.bo;
+ drm_intel_bo *bo = brw->batch.bo;
int chipset_max_threads;
- bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+ bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
sizeof(*sf), 64, &brw->sf.state_offset);
sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
sf->thread3.dispatch_grf_start_reg = 3;
-
- sf->thread3.urb_entry_read_offset =
- brw_sf_compute_urb_entry_read_offset(intel);
+ sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
/* CACHE_NEW_SF_PROG */
sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
/* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
* 48 (Ironlake) threads.
*/
- if (intel->gen == 5)
+ if (brw->gen == 5)
chipset_max_threads = 48;
else
chipset_max_threads = 24;
sf->thread4.stats_enable = 1;
/* CACHE_NEW_SF_VP */
- sf->sf5.sf_viewport_state_offset = (intel->batch.bo->offset +
+ sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset +
brw->sf.vp_offset) >> 5; /* reloc */
sf->sf5.viewport_transform = 1;
/* Emit SF viewport relocation */
drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
offsetof(struct brw_sf_unit_state, sf5)),
- intel->batch.bo, (brw->sf.vp_offset |
+ brw->batch.bo, (brw->sf.vp_offset |
sf->sf5.front_winding |
(sf->sf5.viewport_transform << 1)),
I915_GEM_DOMAIN_INSTRUCTION, 0);