i965/vec4: Make with_writemask() non-static.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_sf_state.c
index f8b5275561d442e3ef63ee090c19b8034e6526ec..4bed5503ff11a5da0cee3ccef16b51f3bce1dbc9 100644 (file)
    
 
 
+#include "main/mtypes.h"
+#include "main/macros.h"
+#include "main/fbobject.h"
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
-#include "main/macros.h"
+#include "brw_sf.h"
 
 static void upload_sf_vp(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
-   struct brw_sf_viewport sfv_stack, *sfv = &sfv_stack;
+   struct brw_sf_viewport *sfv;
    GLfloat y_scale, y_bias;
-   const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
    const GLfloat *v = ctx->Viewport._WindowMap.m;
 
+   sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
+                        sizeof(*sfv), 32, &brw->sf.vp_offset);
    memset(sfv, 0, sizeof(*sfv));
 
    if (render_to_fbo) {
@@ -104,8 +109,7 @@ static void upload_sf_vp(struct brw_context *brw)
       sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
    }
 
-   drm_intel_bo_unreference(brw->sf.vp_bo);
-   brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP, sfv, sizeof(*sfv));
+   brw->state.dirty.cache |= CACHE_NEW_SF_VP;
 }
 
 const struct brw_tracked_state brw_sf_vp = {
@@ -113,37 +117,38 @@ const struct brw_tracked_state brw_sf_vp = {
       .mesa  = (_NEW_VIEWPORT | 
                _NEW_SCISSOR |
                _NEW_BUFFERS),
-      .brw   = 0,
+      .brw   = BRW_NEW_BATCH,
       .cache = 0
    },
-   .prepare = upload_sf_vp
+   .emit = upload_sf_vp
 };
 
 static void upload_sf_unit( struct brw_context *brw )
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    struct brw_sf_unit_state *sf;
-   drm_intel_bo *bo = intel->batch.bo;
+   drm_intel_bo *bo = brw->batch.bo;
    int chipset_max_threads;
-   bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
 
-   sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
+   sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
+                       sizeof(*sf), 64, &brw->sf.state_offset);
 
    memset(sf, 0, sizeof(*sf));
 
-   /* CACHE_NEW_SF_PROG */
+   /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_SF_PROG */
    sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
-   sf->thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
+   sf->thread0.kernel_start_pointer =
+      brw_program_reloc(brw,
+                       brw->sf.state_offset +
+                       offsetof(struct brw_sf_unit_state, thread0),
+                       brw->sf.prog_offset +
+                       (sf->thread0.grf_reg_count << 1)) >> 6;
 
    sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 
    sf->thread3.dispatch_grf_start_reg = 3;
-
-   if (intel->gen == 5)
-       sf->thread3.urb_entry_read_offset = 3;
-   else
-       sf->thread3.urb_entry_read_offset = 1;
+   sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
 
    /* CACHE_NEW_SF_PROG */
    sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
@@ -155,7 +160,7 @@ static void upload_sf_unit( struct brw_context *brw )
    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
     * 48 (Ironlake) threads.
     */
-   if (intel->gen == 5)
+   if (brw->gen == 5)
       chipset_max_threads = 48;
    else
       chipset_max_threads = 24;
@@ -164,14 +169,12 @@ static void upload_sf_unit( struct brw_context *brw )
    sf->thread4.max_threads = MIN2(chipset_max_threads,
                                  brw->urb.nr_sf_entries) - 1;
 
-   if (unlikely(INTEL_DEBUG & DEBUG_SINGLE_THREAD))
-      sf->thread4.max_threads = 0;
-
    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
       sf->thread4.stats_enable = 1;
 
    /* CACHE_NEW_SF_VP */
-   sf->sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset >> 5; /* reloc */
+   sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset +
+                                      brw->sf.vp_offset) >> 5; /* reloc */
 
    sf->sf5.viewport_transform = 1;
 
@@ -254,6 +257,7 @@ static void upload_sf_unit( struct brw_context *brw )
    sf->sf7.point_size = CLAMP(rint(CLAMP(ctx->Point.Size,
                                         ctx->Point.MinSize,
                                         ctx->Point.MaxSize)), 1, 255) * (1<<3);
+   /* _NEW_PROGRAM | _NEW_POINT */
    sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
                                    ctx->Point._Attenuated);
    sf->sf7.aa_line_distance_mode = 0;
@@ -280,17 +284,13 @@ static void upload_sf_unit( struct brw_context *brw )
    /* STATE_PREFETCH command description describes this state as being
     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
     */
-   /* Emit SF program relocation */
-   drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
-                               offsetof(struct brw_sf_unit_state, thread0)),
-                          brw->sf.prog_bo, sf->thread0.grf_reg_count << 1,
-                          I915_GEM_DOMAIN_INSTRUCTION, 0);
 
    /* Emit SF viewport relocation */
    drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
                                offsetof(struct brw_sf_unit_state, sf5)),
-                          brw->sf.vp_bo, (sf->sf5.front_winding |
-                                          (sf->sf5.viewport_transform << 1)),
+                          brw->batch.bo, (brw->sf.vp_offset |
+                                            sf->sf5.front_winding |
+                                            (sf->sf5.viewport_transform << 1)),
                           I915_GEM_DOMAIN_INSTRUCTION, 0);
 
    brw->state.dirty.cache |= CACHE_NEW_SF_UNIT;
@@ -299,15 +299,17 @@ static void upload_sf_unit( struct brw_context *brw )
 const struct brw_tracked_state brw_sf_unit = {
    .dirty = {
       .mesa  = (_NEW_POLYGON | 
+               _NEW_PROGRAM |
                _NEW_LIGHT |
                _NEW_LINE | 
                _NEW_POINT | 
                _NEW_SCISSOR |
                _NEW_BUFFERS),
       .brw   = (BRW_NEW_BATCH |
+               BRW_NEW_PROGRAM_CACHE |
                BRW_NEW_URB_FENCE),
       .cache = (CACHE_NEW_SF_VP |
                CACHE_NEW_SF_PROG)
    },
-   .prepare = upload_sf_unit,
+   .emit = upload_sf_unit,
 };