i965/vec4: Add support for nonconst sampler indexing in VS visitor
[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.cpp
index b38032ec70fbf3b9c4f0e4d1abaced4b79b9894c..00331351c11206dcb331d316ecef66142bd0a6ef 100644 (file)
@@ -28,6 +28,7 @@ extern "C" {
 #include "brw_vs.h"
 #include "brw_vec4_gs.h"
 #include "brw_fs.h"
+#include "brw_cfg.h"
 #include "glsl/ir_optimization.h"
 #include "glsl/glsl_parser_extras.h"
 #include "main/shaderapi.h"
@@ -120,6 +121,8 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
    unsigned int stage;
 
    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
+      const struct gl_shader_compiler_options *options =
+         &ctx->Const.ShaderCompilerOptions[stage];
       struct brw_shader *shader =
         (struct brw_shader *)shProg->_LinkedShaders[stage];
 
@@ -145,7 +148,6 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
       const int bitfield_insert = brw->gen >= 7
                                   ? BITFIELD_INSERT_TO_BFM_BFI
                                   : 0;
-      const int lrp_to_arith = brw->gen < 6 ? LRP_TO_ARITH : 0;
       lower_instructions(shader->base.ir,
                         MOD_TO_FRACT |
                         DIV_TO_MUL_RCP |
@@ -153,7 +155,6 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
                         EXP_TO_EXP2 |
                         LOG_TO_LOG2 |
                          bitfield_insert |
-                         lrp_to_arith |
                          LDEXP_TO_ARITH);
 
       /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
@@ -167,26 +168,23 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
       do_vec_index_to_cond_assign(shader->base.ir);
       lower_vector_insert(shader->base.ir, true);
       brw_do_cubemap_normalize(shader->base.ir);
-      brw_do_lower_offset_arrays(shader->base.ir);
+      lower_offset_arrays(shader->base.ir);
       brw_do_lower_unnormalized_offset(shader->base.ir);
       lower_noise(shader->base.ir);
       lower_quadop_vector(shader->base.ir, false);
 
-      bool input = true;
-      bool output = stage == MESA_SHADER_FRAGMENT;
-      bool temp = stage == MESA_SHADER_FRAGMENT;
-      bool uniform = false;
-
       bool lowered_variable_indexing =
          lower_variable_index_to_cond_assign(shader->base.ir,
-                                             input, output, temp, uniform);
+                                             options->EmitNoIndirectInput,
+                                             options->EmitNoIndirectOutput,
+                                             options->EmitNoIndirectTemp,
+                                             options->EmitNoIndirectUniform);
 
       if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
          perf_debug("Unsupported form of variable indexing in FS; falling "
                     "back to very inefficient code generation\n");
       }
 
-      /* FINISHME: Do this before the variable index lowering. */
       lower_ubo_reference(&shader->base, shader->base.ir);
 
       do {
@@ -203,8 +201,8 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
                                   false /* loops */
                                   ) || progress;
 
-        progress = do_common_optimization(shader->base.ir, true, true, 32,
-                                           &ctx->ShaderCompilerOptions[stage])
+        progress = do_common_optimization(shader->base.ir, true, true,
+                                           options, ctx->Const.NativeIntegers)
           || progress;
       } while (progress);
 
@@ -215,8 +213,8 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
        * too late.  At that point, the values for the built-in uniforms won't
        * get sent to the shader.
        */
-      foreach_list(node, shader->base.ir) {
-        ir_variable *var = ((ir_instruction *) node)->as_variable();
+      foreach_in_list(ir_instruction, node, shader->base.ir) {
+        ir_variable *var = node->as_variable();
 
         if ((var == NULL) || (var->data.mode != ir_var_uniform)
             || (strncmp(var->name, "gl_", 3) != 0))
@@ -250,28 +248,27 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 
       _mesa_reference_program(ctx, &prog, NULL);
 
-      if (ctx->Shader.Flags & GLSL_DUMP) {
-         printf("\n");
-         printf("GLSL IR for linked %s program %d:\n",
-                _mesa_shader_stage_to_string(shader->base.Stage),
-                shProg->Name);
-         _mesa_print_ir(shader->base.ir, NULL);
-         printf("\n");
+      if (ctx->_Shader->Flags & GLSL_DUMP) {
+         fprintf(stderr, "\n");
+         fprintf(stderr, "GLSL IR for linked %s program %d:\n",
+                 _mesa_shader_stage_to_string(shader->base.Stage),
+                 shProg->Name);
+         _mesa_print_ir(stderr, shader->base.ir, NULL);
+         fprintf(stderr, "\n");
       }
    }
 
-   if (ctx->Shader.Flags & GLSL_DUMP) {
+   if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
       for (unsigned i = 0; i < shProg->NumShaders; i++) {
          const struct gl_shader *sh = shProg->Shaders[i];
          if (!sh)
             continue;
 
-         printf("GLSL %s shader %d source for linked program %d:\n",
-                _mesa_shader_stage_to_string(sh->Stage),
-                i,
-                shProg->Name);
-         printf("%s", sh->Source);
-         printf("\n");
+         fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
+                 _mesa_shader_stage_to_string(sh->Stage),
+                 i, shProg->Name);
+         fprintf(stderr, "%s", sh->Source);
+         fprintf(stderr, "\n");
       }
    }
 
@@ -282,7 +279,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 }
 
 
-int
+enum brw_reg_type
 brw_type_for_base_type(const struct glsl_type *type)
 {
    switch (type->base_type) {
@@ -303,17 +300,18 @@ brw_type_for_base_type(const struct glsl_type *type)
        * way to trip up if we don't.
        */
       return BRW_REGISTER_TYPE_UD;
+   case GLSL_TYPE_IMAGE:
+      return BRW_REGISTER_TYPE_UD;
    case GLSL_TYPE_VOID:
    case GLSL_TYPE_ERROR:
    case GLSL_TYPE_INTERFACE:
-      assert(!"not reached");
-      break;
+      unreachable("not reached");
    }
 
    return BRW_REGISTER_TYPE_F;
 }
 
-uint32_t
+enum brw_conditional_mod
 brw_conditional_for_comparison(unsigned int op)
 {
    switch (op) {
@@ -332,8 +330,7 @@ brw_conditional_for_comparison(unsigned int op)
    case ir_binop_any_nequal: /* same as nequal for scalars */
       return BRW_CONDITIONAL_NZ;
    default:
-      assert(!"not reached: bad operation for comparison");
-      return BRW_CONDITIONAL_NZ;
+      unreachable("not reached: bad operation for comparison");
    }
 }
 
@@ -362,8 +359,7 @@ brw_math_function(enum opcode op)
    case SHADER_OPCODE_INT_REMAINDER:
       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
    default:
-      assert(!"not reached: unknown math function");
-      return 0;
+      unreachable("not reached: unknown math function");
    }
 }
 
@@ -406,6 +402,8 @@ brw_instruction_name(enum opcode op)
    switch (op) {
    case FS_OPCODE_FB_WRITE:
       return "fb_write";
+   case FS_OPCODE_BLORP_FB_WRITE:
+      return "blorp_fb_write";
 
    case SHADER_OPCODE_RCP:
       return "rcp";
@@ -450,6 +448,11 @@ brw_instruction_name(enum opcode op)
       return "tg4";
    case SHADER_OPCODE_TG4_OFFSET:
       return "tg4_offset";
+   case SHADER_OPCODE_SHADER_TIME_ADD:
+      return "shader_time_add";
+
+   case SHADER_OPCODE_LOAD_PAYLOAD:
+      return "load_payload";
 
    case SHADER_OPCODE_GEN4_SCRATCH_READ:
       return "gen4_scratch_read";
@@ -523,6 +526,8 @@ brw_instruction_name(enum opcode op)
       return "prepare_channel_masks";
    case GS_OPCODE_SET_CHANNEL_MASKS:
       return "set_channel_masks";
+   case GS_OPCODE_GET_INSTANCE_ID:
+      return "get_instance_id";
 
    default:
       /* Yes, this leaks.  It's in debug code, it should never occur, and if
@@ -533,8 +538,62 @@ brw_instruction_name(enum opcode op)
    }
 }
 
+backend_visitor::backend_visitor(struct brw_context *brw,
+                                 struct gl_shader_program *shader_prog,
+                                 struct gl_program *prog,
+                                 struct brw_stage_prog_data *stage_prog_data,
+                                 gl_shader_stage stage)
+   : brw(brw),
+     ctx(&brw->ctx),
+     shader(shader_prog ?
+        (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
+     shader_prog(shader_prog),
+     prog(prog),
+     stage_prog_data(stage_prog_data),
+     cfg(NULL),
+     stage(stage)
+{
+}
+
+bool
+backend_reg::is_zero() const
+{
+   if (file != IMM)
+      return false;
+
+   return fixed_hw_reg.dw1.d == 0;
+}
+
+bool
+backend_reg::is_one() const
+{
+   if (file != IMM)
+      return false;
+
+   return type == BRW_REGISTER_TYPE_F
+          ? fixed_hw_reg.dw1.f == 1.0
+          : fixed_hw_reg.dw1.d == 1;
+}
+
+bool
+backend_reg::is_null() const
+{
+   return file == HW_REG &&
+          fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+          fixed_hw_reg.nr == BRW_ARF_NULL;
+}
+
+
+bool
+backend_reg::is_accumulator() const
+{
+   return file == HW_REG &&
+          fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+          fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
+}
+
 bool
-backend_instruction::is_tex()
+backend_instruction::is_tex() const
 {
    return (opcode == SHADER_OPCODE_TEX ||
            opcode == FS_OPCODE_TXB ||
@@ -551,7 +610,7 @@ backend_instruction::is_tex()
 }
 
 bool
-backend_instruction::is_math()
+backend_instruction::is_math() const
 {
    return (opcode == SHADER_OPCODE_RCP ||
            opcode == SHADER_OPCODE_RSQ ||
@@ -566,7 +625,7 @@ backend_instruction::is_math()
 }
 
 bool
-backend_instruction::is_control_flow()
+backend_instruction::is_control_flow() const
 {
    switch (opcode) {
    case BRW_OPCODE_DO:
@@ -583,7 +642,7 @@ backend_instruction::is_control_flow()
 }
 
 bool
-backend_instruction::can_do_source_mods()
+backend_instruction::can_do_source_mods() const
 {
    switch (opcode) {
    case BRW_OPCODE_ADDC:
@@ -601,6 +660,73 @@ backend_instruction::can_do_source_mods()
    }
 }
 
+bool
+backend_instruction::can_do_saturate() const
+{
+   switch (opcode) {
+   case BRW_OPCODE_ADD:
+   case BRW_OPCODE_ASR:
+   case BRW_OPCODE_AVG:
+   case BRW_OPCODE_DP2:
+   case BRW_OPCODE_DP3:
+   case BRW_OPCODE_DP4:
+   case BRW_OPCODE_DPH:
+   case BRW_OPCODE_F16TO32:
+   case BRW_OPCODE_F32TO16:
+   case BRW_OPCODE_LINE:
+   case BRW_OPCODE_LRP:
+   case BRW_OPCODE_MAC:
+   case BRW_OPCODE_MACH:
+   case BRW_OPCODE_MAD:
+   case BRW_OPCODE_MATH:
+   case BRW_OPCODE_MOV:
+   case BRW_OPCODE_MUL:
+   case BRW_OPCODE_PLN:
+   case BRW_OPCODE_RNDD:
+   case BRW_OPCODE_RNDE:
+   case BRW_OPCODE_RNDU:
+   case BRW_OPCODE_RNDZ:
+   case BRW_OPCODE_SEL:
+   case BRW_OPCODE_SHL:
+   case BRW_OPCODE_SHR:
+   case FS_OPCODE_LINTERP:
+   case SHADER_OPCODE_COS:
+   case SHADER_OPCODE_EXP2:
+   case SHADER_OPCODE_LOG2:
+   case SHADER_OPCODE_POW:
+   case SHADER_OPCODE_RCP:
+   case SHADER_OPCODE_RSQ:
+   case SHADER_OPCODE_SIN:
+   case SHADER_OPCODE_SQRT:
+      return true;
+   default:
+      return false;
+   }
+}
+
+bool
+backend_instruction::reads_accumulator_implicitly() const
+{
+   switch (opcode) {
+   case BRW_OPCODE_MAC:
+   case BRW_OPCODE_MACH:
+   case BRW_OPCODE_SADA2:
+      return true;
+   default:
+      return false;
+   }
+}
+
+bool
+backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
+{
+   return writes_accumulator ||
+          (brw->gen < 6 &&
+           ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
+            (opcode >= FS_OPCODE_DDX && opcode <= FS_OPCODE_LINTERP &&
+             opcode != FS_OPCODE_CINTERP)));
+}
+
 bool
 backend_instruction::has_side_effects() const
 {
@@ -615,14 +741,45 @@ backend_instruction::has_side_effects() const
 void
 backend_visitor::dump_instructions()
 {
+   dump_instructions(NULL);
+}
+
+void
+backend_visitor::dump_instructions(const char *name)
+{
+   FILE *file = stderr;
+   if (name && geteuid() != 0) {
+      file = fopen(name, "w");
+      if (!file)
+         file = stderr;
+   }
+
    int ip = 0;
-   foreach_list(node, &this->instructions) {
-      backend_instruction *inst = (backend_instruction *)node;
-      printf("%d: ", ip++);
-      dump_instruction(inst);
+   foreach_in_list(backend_instruction, inst, &instructions) {
+      if (!name)
+         fprintf(stderr, "%d: ", ip++);
+      dump_instruction(inst, file);
+   }
+
+   if (file != stderr) {
+      fclose(file);
    }
 }
 
+void
+backend_visitor::calculate_cfg()
+{
+   if (this->cfg)
+      return;
+   cfg = new(mem_ctx) cfg_t(&this->instructions);
+}
+
+void
+backend_visitor::invalidate_cfg()
+{
+   ralloc_free(this->cfg);
+   this->cfg = NULL;
+}
 
 /**
  * Sets up the starting offsets for the groups of binding table entries
@@ -655,8 +812,13 @@ backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table
    }
 
    if (prog->UsesGather) {
-      stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
-      next_binding_table_offset += num_textures;
+      if (brw->gen >= 8) {
+         stage_prog_data->binding_table.gather_texture_start =
+            stage_prog_data->binding_table.texture_start;
+      } else {
+         stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
+         next_binding_table_offset += num_textures;
+      }
    } else {
       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
    }
@@ -674,5 +836,5 @@ backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table
 
    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 
-   /* prog_data->base.binding_table.size will be set by mark_surface_used. */
+   /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 }