#include "brw_fs.h"
#include "brw_nir.h"
#include "brw_vec4_tes.h"
-#include "main/shaderobj.h"
#include "main/uniforms.h"
-extern "C" struct gl_shader *
-brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
-{
- struct brw_shader *shader;
-
- shader = rzalloc(NULL, struct brw_shader);
- if (shader) {
- shader->base.Type = type;
- shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
- shader->base.Name = name;
- _mesa_init_shader(ctx, &shader->base);
- }
-
- return &shader->base;
-}
-
extern "C" void
brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
unsigned surf_index)
return BRW_REGISTER_TYPE_UD;
case GLSL_TYPE_IMAGE:
return BRW_REGISTER_TYPE_UD;
+ case GLSL_TYPE_DOUBLE:
+ return BRW_REGISTER_TYPE_DF;
+ case GLSL_TYPE_UINT64:
+ return BRW_REGISTER_TYPE_UQ;
+ case GLSL_TYPE_INT64:
+ return BRW_REGISTER_TYPE_Q;
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
- case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_FUNCTION:
unreachable("not reached");
}
}
}
-uint32_t
-brw_texture_offset(int *offsets, unsigned num_components)
+bool
+brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
{
- if (!offsets) return 0; /* nonconstant offset; caller will handle it. */
+ if (!offsets) return false; /* nonconstant offset; caller will handle it. */
+
+ /* offset out of bounds; caller will handle it. */
+ for (unsigned i = 0; i < num_components; i++)
+ if (offsets[i] > 7 || offsets[i] < -8)
+ return false;
/* Combine all three offsets into a single unsigned dword:
*
* bits 7:4 - V Offset (Y component)
* bits 3:0 - R Offset (Z component)
*/
- unsigned offset_bits = 0;
+ *offset_bits = 0;
for (unsigned i = 0; i < num_components; i++) {
const unsigned shift = 4 * (2 - i);
- offset_bits |= (offsets[i] << shift) & (0xF << shift);
+ *offset_bits |= (offsets[i] << shift) & (0xF << shift);
}
- return offset_bits;
+ return true;
}
const char *
-brw_instruction_name(enum opcode op)
+brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
{
switch (op) {
case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
- assert(opcode_descs[op].name);
- return opcode_descs[op].name;
+ /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
+ * start of a loop in the IR.
+ */
+ if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
+ return "do";
+
+ assert(brw_opcode_desc(devinfo, op)->name);
+ return brw_opcode_desc(devinfo, op)->name;
case FS_OPCODE_FB_WRITE:
return "fb_write";
case FS_OPCODE_FB_WRITE_LOGICAL:
return "fb_write_logical";
- case FS_OPCODE_PACK_STENCIL_REF:
- return "pack_stencil_ref";
- case FS_OPCODE_BLORP_FB_WRITE:
- return "blorp_fb_write";
case FS_OPCODE_REP_FB_WRITE:
return "rep_fb_write";
+ case FS_OPCODE_FB_READ:
+ return "fb_read";
+ case FS_OPCODE_FB_READ_LOGICAL:
+ return "fb_read_logical";
case SHADER_OPCODE_RCP:
return "rcp";
return "txf";
case SHADER_OPCODE_TXF_LOGICAL:
return "txf_logical";
+ case SHADER_OPCODE_TXF_LZ:
+ return "txf_lz";
case SHADER_OPCODE_TXL:
return "txl";
case SHADER_OPCODE_TXL_LOGICAL:
return "txl_logical";
+ case SHADER_OPCODE_TXL_LZ:
+ return "txl_lz";
case SHADER_OPCODE_TXS:
return "txs";
case SHADER_OPCODE_TXS_LOGICAL:
return "tg4_offset_logical";
case SHADER_OPCODE_SAMPLEINFO:
return "sampleinfo";
+ case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
+ return "sampleinfo_logical";
case SHADER_OPCODE_SHADER_TIME_ADD:
return "shader_time_add";
case SHADER_OPCODE_LOAD_PAYLOAD:
return "load_payload";
+ case FS_OPCODE_PACK:
+ return "pack";
case SHADER_OPCODE_GEN4_SCRATCH_READ:
return "gen4_scratch_read";
case SHADER_OPCODE_BROADCAST:
return "broadcast";
- case SHADER_OPCODE_EXTRACT_BYTE:
- return "extract_byte";
- case SHADER_OPCODE_EXTRACT_WORD:
- return "extract_word";
case VEC4_OPCODE_MOV_BYTES:
return "mov_bytes";
case VEC4_OPCODE_PACK_BYTES:
return "pack_bytes";
case VEC4_OPCODE_UNPACK_UNIFORM:
return "unpack_uniform";
+ case VEC4_OPCODE_FROM_DOUBLE:
+ return "double_to_single";
+ case VEC4_OPCODE_TO_DOUBLE:
+ return "single_to_double";
+ case VEC4_OPCODE_PICK_LOW_32BIT:
+ return "pick_low_32bit";
+ case VEC4_OPCODE_PICK_HIGH_32BIT:
+ return "pick_high_32bit";
+ case VEC4_OPCODE_SET_LOW_32BIT:
+ return "set_low_32bit";
+ case VEC4_OPCODE_SET_HIGH_32BIT:
+ return "set_high_32bit";
case FS_OPCODE_DDX_COARSE:
return "ddx_coarse";
return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
return "uniform_pull_const_gen7";
- case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
- return "varying_pull_const";
+ case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
+ return "varying_pull_const_gen4";
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
return "varying_pull_const_gen7";
+ case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
+ return "varying_pull_const_logical";
case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
return "mov_dispatch_to_flags";
case FS_OPCODE_SET_SAMPLE_ID:
return "set_sample_id";
- case FS_OPCODE_SET_SIMD4X2_OFFSET:
- return "set_simd4x2_offset";
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
return "pack_half_2x16_split";
case FS_OPCODE_PLACEHOLDER_HALT:
return "placeholder_halt";
- case FS_OPCODE_INTERPOLATE_AT_CENTROID:
- return "interp_centroid";
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
return "interp_sample";
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
unsigned ud;
int d;
float f;
- } imm = { reg->ud }, sat_imm = { 0 };
+ double df;
+ } imm, sat_imm = { 0 };
+
+ const unsigned size = type_sz(type);
+
+ /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
+ * irrelevant, so just check the size of the type and copy from/to an
+ * appropriately sized field.
+ */
+ if (size < 8)
+ imm.ud = reg->ud;
+ else
+ imm.df = reg->df;
switch (type) {
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_F:
sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
break;
+ case BRW_REGISTER_TYPE_DF:
+ sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
+ break;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_VF:
unreachable("unimplemented: saturate vector immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- unreachable("unimplemented: saturate DF/HF immediate");
+ unreachable("unimplemented: saturate HF immediate");
}
- if (imm.ud != sat_imm.ud) {
- reg->ud = sat_imm.ud;
- return true;
+ if (size < 8) {
+ if (imm.ud != sat_imm.ud) {
+ reg->ud = sat_imm.ud;
+ return true;
+ }
+ } else {
+ if (imm.df != sat_imm.df) {
+ reg->df = sat_imm.df;
+ return true;
+ }
}
return false;
}
case BRW_REGISTER_TYPE_VF:
reg->ud ^= 0x80808080;
return true;
+ case BRW_REGISTER_TYPE_DF:
+ reg->df = -reg->df;
+ return true;
+ case BRW_REGISTER_TYPE_UQ:
+ case BRW_REGISTER_TYPE_Q:
+ reg->d64 = -reg->d64;
+ return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_V:
assert(!"unimplemented: negate UV/V immediate");
- case BRW_REGISTER_TYPE_UQ:
- case BRW_REGISTER_TYPE_Q:
- assert(!"unimplemented: negate UQ/Q immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- assert(!"unimplemented: negate DF/HF immediate");
+ assert(!"unimplemented: negate HF immediate");
}
return false;
case BRW_REGISTER_TYPE_F:
reg->f = fabsf(reg->f);
return true;
+ case BRW_REGISTER_TYPE_DF:
+ reg->df = fabs(reg->df);
+ return true;
case BRW_REGISTER_TYPE_VF:
reg->ud &= ~0x80808080;
return true;
+ case BRW_REGISTER_TYPE_Q:
+ reg->d64 = imaxabs(reg->d64);
+ return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
unreachable("no UB/B immediates");
assert(!"unimplemented: abs unsigned immediate");
case BRW_REGISTER_TYPE_V:
assert(!"unimplemented: abs V immediate");
- case BRW_REGISTER_TYPE_Q:
- assert(!"unimplemented: abs Q immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- assert(!"unimplemented: abs DF/HF immediate");
+ assert(!"unimplemented: abs HF immediate");
}
return false;
}
+/**
+ * Get the appropriate atomic op for an image atomic intrinsic.
+ */
+unsigned
+get_atomic_counter_op(nir_intrinsic_op op)
+{
+ switch (op) {
+ case nir_intrinsic_atomic_counter_inc:
+ return BRW_AOP_INC;
+ case nir_intrinsic_atomic_counter_dec:
+ return BRW_AOP_PREDEC;
+ case nir_intrinsic_atomic_counter_add:
+ return BRW_AOP_ADD;
+ case nir_intrinsic_atomic_counter_min:
+ return BRW_AOP_UMIN;
+ case nir_intrinsic_atomic_counter_max:
+ return BRW_AOP_UMAX;
+ case nir_intrinsic_atomic_counter_and:
+ return BRW_AOP_AND;
+ case nir_intrinsic_atomic_counter_or:
+ return BRW_AOP_OR;
+ case nir_intrinsic_atomic_counter_xor:
+ return BRW_AOP_XOR;
+ case nir_intrinsic_atomic_counter_exchange:
+ return BRW_AOP_MOV;
+ case nir_intrinsic_atomic_counter_comp_swap:
+ return BRW_AOP_CMPWR;
+ default:
+ unreachable("Not reachable.");
+ }
+}
+
backend_shader::backend_shader(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
bool
backend_reg::equals(const backend_reg &r) const
{
- return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
- reg_offset == r.reg_offset;
+ return brw_regs_equal(this, &r) && offset == r.offset;
}
bool
if (file != IMM)
return false;
- return d == 0;
+ switch (type) {
+ case BRW_REGISTER_TYPE_F:
+ return f == 0;
+ case BRW_REGISTER_TYPE_DF:
+ return df == 0;
+ case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UD:
+ return d == 0;
+ case BRW_REGISTER_TYPE_UQ:
+ case BRW_REGISTER_TYPE_Q:
+ return u64 == 0;
+ default:
+ return false;
+ }
}
bool
if (file != IMM)
return false;
- return type == BRW_REGISTER_TYPE_F
- ? f == 1.0
- : d == 1;
+ switch (type) {
+ case BRW_REGISTER_TYPE_F:
+ return f == 1.0f;
+ case BRW_REGISTER_TYPE_DF:
+ return df == 1.0;
+ case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UD:
+ return d == 1;
+ case BRW_REGISTER_TYPE_UQ:
+ case BRW_REGISTER_TYPE_Q:
+ return u64 == 1;
+ default:
+ return false;
+ }
}
bool
switch (type) {
case BRW_REGISTER_TYPE_F:
return f == -1.0;
+ case BRW_REGISTER_TYPE_DF:
+ return df == -1.0;
case BRW_REGISTER_TYPE_D:
return d == -1;
+ case BRW_REGISTER_TYPE_Q:
+ return d64 == -1;
default:
return false;
}
return file == ARF && nr == BRW_ARF_ACCUMULATOR;
}
-bool
-backend_reg::in_range(const backend_reg &r, unsigned n) const
-{
- return (file == r.file &&
- nr == r.nr &&
- reg_offset >= r.reg_offset &&
- reg_offset < r.reg_offset + n);
-}
-
bool
backend_instruction::is_commutative() const
{
}
bool
-backend_instruction::is_3src() const
+backend_instruction::is_3src(const struct gen_device_info *devinfo) const
{
- return ::is_3src(opcode);
+ return ::is_3src(devinfo, opcode);
}
bool
opcode == FS_OPCODE_TXB ||
opcode == SHADER_OPCODE_TXD ||
opcode == SHADER_OPCODE_TXF ||
+ opcode == SHADER_OPCODE_TXF_LZ ||
opcode == SHADER_OPCODE_TXF_CMS ||
opcode == SHADER_OPCODE_TXF_CMS_W ||
opcode == SHADER_OPCODE_TXF_UMS ||
opcode == SHADER_OPCODE_TXF_MCS ||
opcode == SHADER_OPCODE_TXL ||
+ opcode == SHADER_OPCODE_TXL_LZ ||
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD ||
opcode == SHADER_OPCODE_TG4 ||
- opcode == SHADER_OPCODE_TG4_OFFSET);
+ opcode == SHADER_OPCODE_TG4_OFFSET ||
+ opcode == SHADER_OPCODE_SAMPLEINFO);
}
bool
}
bool
-backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
+backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
{
return writes_accumulator ||
(devinfo->gen < 6 &&
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
case FS_OPCODE_FB_WRITE:
+ case FS_OPCODE_FB_WRITE_LOGICAL:
case SHADER_OPCODE_BARRIER:
case TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT:
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_READ:
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
+ case SHADER_OPCODE_URB_READ_SIMD8:
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
+ case VEC4_OPCODE_URB_READ:
return true;
default:
return false;
adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
{
for (bblock_t *block_iter = start_block->next();
- !block_iter->link.is_tail_sentinel();
+ block_iter;
block_iter = block_iter->next()) {
block_iter->start_ip += ip_adjustment;
block_iter->end_ip += ip_adjustment;
void
backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
{
+ assert(this != inst);
+
if (!this->is_head_sentinel())
assert(inst_is_in_block(block, this) || !"Instruction not in block");
void
backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
{
+ assert(this != inst);
+
if (!this->is_tail_sentinel())
assert(inst_is_in_block(block, this) || !"Instruction not in block");
cfg = new(mem_ctx) cfg_t(&this->instructions);
}
-void
-backend_shader::invalidate_cfg()
-{
- ralloc_free(this->cfg);
- this->cfg = NULL;
-}
-
/**
* Sets up the starting offsets for the groups of binding table entries
* commong to all pipeline stages.
* unused but also make sure that addition of small offsets to them will
* trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
*/
-void
-brw_assign_common_binding_table_offsets(gl_shader_stage stage,
- const struct brw_device_info *devinfo,
- const struct gl_shader_program *shader_prog,
+uint32_t
+brw_assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
uint32_t next_binding_table_offset)
{
- const struct gl_shader *shader = NULL;
- int num_textures = _mesa_fls(prog->SamplersUsed);
-
- if (shader_prog)
- shader = shader_prog->_LinkedShaders[stage];
+ int num_textures = util_last_bit(prog->SamplersUsed);
stage_prog_data->binding_table.texture_start = next_binding_table_offset;
next_binding_table_offset += num_textures;
- if (shader) {
- assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
+ if (prog->info.num_ubos) {
+ assert(prog->info.num_ubos <= BRW_MAX_UBO);
stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
- next_binding_table_offset += shader->NumUniformBlocks;
+ next_binding_table_offset += prog->info.num_ubos;
+ } else {
+ stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
+ }
- assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
+ if (prog->info.num_ssbos) {
+ assert(prog->info.num_ssbos <= BRW_MAX_SSBO);
stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
- next_binding_table_offset += shader->NumShaderStorageBlocks;
+ next_binding_table_offset += prog->info.num_ssbos;
} else {
- stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
}
stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
}
- if (prog->UsesGather) {
+ if (prog->nir->info->uses_texture_gather) {
if (devinfo->gen >= 8) {
stage_prog_data->binding_table.gather_texture_start =
stage_prog_data->binding_table.texture_start;
stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
}
- if (shader && shader->NumAtomicBuffers) {
+ if (prog->info.num_abos) {
stage_prog_data->binding_table.abo_start = next_binding_table_offset;
- next_binding_table_offset += shader->NumAtomicBuffers;
+ next_binding_table_offset += prog->info.num_abos;
} else {
stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
}
- if (shader && shader->NumImages) {
+ if (prog->info.num_images) {
stage_prog_data->binding_table.image_start = next_binding_table_offset;
- next_binding_table_offset += shader->NumImages;
+ next_binding_table_offset += prog->info.num_images;
} else {
stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
}
stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
next_binding_table_offset++;
- assert(next_binding_table_offset <= BRW_MAX_SURFACES);
+ /* Plane 0 is just the regular texture section */
+ stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
+
+ stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
+
+ stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
+
+ assert(next_binding_table_offset <= BRW_MAX_SURFACES);
+ return next_binding_table_offset;
}
static void
void *log_data,
void *mem_ctx,
const struct brw_tes_prog_key *key,
+ const struct brw_vue_map *input_vue_map,
struct brw_tes_prog_data *prog_data,
const nir_shader *src_shader,
- struct gl_shader_program *shader_prog,
+ struct gl_program *prog,
int shader_time_index,
unsigned *final_assembly_size,
char **error_str)
{
- const struct brw_device_info *devinfo = compiler->devinfo;
- struct gl_shader *shader =
- shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
+ const struct gen_device_info *devinfo = compiler->devinfo;
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
- nir->info.inputs_read = key->inputs_read;
- nir->info.patch_inputs_read = key->patch_inputs_read;
+ nir->info->inputs_read = key->inputs_read;
+ nir->info->patch_inputs_read = key->patch_inputs_read;
- struct brw_vue_map input_vue_map;
- brw_compute_tess_vue_map(&input_vue_map,
- nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
- nir->info.patch_inputs_read);
-
- nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
- brw_nir_lower_tes_inputs(nir, &input_vue_map);
+ nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
+ brw_nir_lower_tes_inputs(nir, input_vue_map);
brw_nir_lower_vue_outputs(nir, is_scalar);
- nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
+ nir = brw_postprocess_nir(nir, compiler, is_scalar);
brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
- nir->info.outputs_written,
- nir->info.separate_shader);
+ nir->info->outputs_written,
+ nir->info->separate_shader);
unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
return NULL;
}
+ prog_data->base.clip_distance_mask =
+ ((1 << nir->info->clip_distance_array_size) - 1);
+ prog_data->base.cull_distance_mask =
+ ((1 << nir->info->cull_distance_array_size) - 1) <<
+ nir->info->clip_distance_array_size;
+
/* URB entry sizes are stored as a multiple of 64 bytes. */
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
+ prog_data->base.urb_read_length = 0;
- bool need_patch_header = nir->info.system_values_read &
- (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
- BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
+ STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
+ STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
+ TESS_SPACING_FRACTIONAL_ODD - 1);
+ STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
+ TESS_SPACING_FRACTIONAL_EVEN - 1);
- /* The TES will pull most inputs using URB read messages.
- *
- * However, we push the patch header for TessLevel factors when required,
- * as it's a tiny amount of extra data.
- */
- prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
+ prog_data->partitioning =
+ (enum brw_tess_partitioning) (nir->info->tess.spacing - 1);
+
+ switch (nir->info->tess.primitive_mode) {
+ case GL_QUADS:
+ prog_data->domain = BRW_TESS_DOMAIN_QUAD;
+ break;
+ case GL_TRIANGLES:
+ prog_data->domain = BRW_TESS_DOMAIN_TRI;
+ break;
+ case GL_ISOLINES:
+ prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
+ break;
+ default:
+ unreachable("invalid domain shader primitive mode");
+ }
+
+ if (nir->info->tess.point_mode) {
+ prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
+ } else if (nir->info->tess.primitive_mode == GL_ISOLINES) {
+ prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
+ } else {
+ /* Hardware winding order is backwards from OpenGL */
+ prog_data->output_topology =
+ nir->info->tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
+ : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
+ }
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
fprintf(stderr, "TES Input ");
- brw_print_vue_map(stderr, &input_vue_map);
+ brw_print_vue_map(stderr, input_vue_map);
fprintf(stderr, "TES Output ");
brw_print_vue_map(stderr, &prog_data->base.vue_map);
}
if (is_scalar) {
fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
- &prog_data->base.base, shader->Program, nir, 8,
- shader_time_index, &input_vue_map);
+ &prog_data->base.base, NULL, nir, 8,
+ shader_time_index, input_vue_map);
if (!v.run_tes()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
return NULL;
}
+ prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_generator g(compiler, log_data, mem_ctx, (void *) key,
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
g.enable_debug(ralloc_asprintf(mem_ctx,
"%s tessellation evaluation shader %s",
- nir->info.label ? nir->info.label
+ nir->info->label ? nir->info->label
: "unnamed",
- nir->info.name));
+ nir->info->name));
}
g.generate_code(v.cfg, 8);
projects / mesa.git / blobdiff