#include "brw_fs.h"
#include "brw_nir.h"
#include "brw_vec4_tes.h"
-#include "main/shaderobj.h"
#include "main/uniforms.h"
-extern "C" struct gl_shader *
-brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
-{
- struct brw_shader *shader;
-
- shader = rzalloc(NULL, struct brw_shader);
- if (shader) {
- shader->base.Type = type;
- shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
- shader->base.Name = name;
- _mesa_init_shader(ctx, &shader->base);
- }
-
- return &shader->base;
-}
-
extern "C" void
brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
unsigned surf_index)
{
switch (op) {
case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
+ /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
+ * start of a loop in the IR.
+ */
+ if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
+ return "do";
+
assert(brw_opcode_desc(devinfo, op)->name);
return brw_opcode_desc(devinfo, op)->name;
case FS_OPCODE_FB_WRITE:
return "fb_write";
case FS_OPCODE_FB_WRITE_LOGICAL:
return "fb_write_logical";
- case FS_OPCODE_PACK_STENCIL_REF:
- return "pack_stencil_ref";
- case FS_OPCODE_BLORP_FB_WRITE:
- return "blorp_fb_write";
case FS_OPCODE_REP_FB_WRITE:
return "rep_fb_write";
+ case FS_OPCODE_FB_READ:
+ return "fb_read";
+ case FS_OPCODE_FB_READ_LOGICAL:
+ return "fb_read_logical";
case SHADER_OPCODE_RCP:
return "rcp";
return "txf";
case SHADER_OPCODE_TXF_LOGICAL:
return "txf_logical";
+ case SHADER_OPCODE_TXF_LZ:
+ return "txf_lz";
case SHADER_OPCODE_TXL:
return "txl";
case SHADER_OPCODE_TXL_LOGICAL:
return "txl_logical";
+ case SHADER_OPCODE_TXL_LZ:
+ return "txl_lz";
case SHADER_OPCODE_TXS:
return "txs";
case SHADER_OPCODE_TXS_LOGICAL:
return "tg4_offset_logical";
case SHADER_OPCODE_SAMPLEINFO:
return "sampleinfo";
+ case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
+ return "sampleinfo_logical";
case SHADER_OPCODE_SHADER_TIME_ADD:
return "shader_time_add";
case SHADER_OPCODE_LOAD_PAYLOAD:
return "load_payload";
+ case FS_OPCODE_PACK:
+ return "pack";
case SHADER_OPCODE_GEN4_SCRATCH_READ:
return "gen4_scratch_read";
case SHADER_OPCODE_BROADCAST:
return "broadcast";
- case SHADER_OPCODE_EXTRACT_BYTE:
- return "extract_byte";
- case SHADER_OPCODE_EXTRACT_WORD:
- return "extract_word";
case VEC4_OPCODE_MOV_BYTES:
return "mov_bytes";
case VEC4_OPCODE_PACK_BYTES:
return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
return "uniform_pull_const_gen7";
- case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
- return "varying_pull_const";
+ case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
+ return "varying_pull_const_gen4";
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
return "varying_pull_const_gen7";
+ case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
+ return "varying_pull_const_logical";
case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
return "mov_dispatch_to_flags";
case FS_OPCODE_PLACEHOLDER_HALT:
return "placeholder_halt";
- case FS_OPCODE_INTERPOLATE_AT_CENTROID:
- return "interp_centroid";
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
return "interp_sample";
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
bool
backend_reg::equals(const backend_reg &r) const
{
- return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
- reg_offset == r.reg_offset;
+ return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
}
bool
opcode == FS_OPCODE_TXB ||
opcode == SHADER_OPCODE_TXD ||
opcode == SHADER_OPCODE_TXF ||
+ opcode == SHADER_OPCODE_TXF_LZ ||
opcode == SHADER_OPCODE_TXF_CMS ||
opcode == SHADER_OPCODE_TXF_CMS_W ||
opcode == SHADER_OPCODE_TXF_UMS ||
opcode == SHADER_OPCODE_TXF_MCS ||
opcode == SHADER_OPCODE_TXL ||
+ opcode == SHADER_OPCODE_TXL_LZ ||
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD ||
opcode == SHADER_OPCODE_TG4 ||
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
case FS_OPCODE_FB_WRITE:
+ case FS_OPCODE_FB_WRITE_LOGICAL:
case SHADER_OPCODE_BARRIER:
case TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT:
* unused but also make sure that addition of small offsets to them will
* trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
*/
-void
+uint32_t
brw_assign_common_binding_table_offsets(gl_shader_stage stage,
const struct brw_device_info *devinfo,
const struct gl_shader_program *shader_prog,
struct brw_stage_prog_data *stage_prog_data,
uint32_t next_binding_table_offset)
{
- const struct gl_shader *shader = NULL;
- int num_textures = _mesa_fls(prog->SamplersUsed);
+ const struct gl_linked_shader *shader = NULL;
+ int num_textures = util_last_bit(prog->SamplersUsed);
if (shader_prog)
shader = shader_prog->_LinkedShaders[stage];
stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
next_binding_table_offset++;
- assert(next_binding_table_offset <= BRW_MAX_SURFACES);
+ /* Plane 0 is just the regular texture section */
+ stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
+
+ stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
+
+ stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
+
+ assert(next_binding_table_offset <= BRW_MAX_SURFACES);
+ return next_binding_table_offset;
}
static void
char **error_str)
{
const struct brw_device_info *devinfo = compiler->devinfo;
- struct gl_shader *shader =
+ struct gl_linked_shader *shader =
shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
return NULL;
}
+ prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_generator g(compiler, log_data, mem_ctx, (void *) key,
projects / mesa.git / blobdiff