* IN THE SOFTWARE.
*/
-#include "main/macros.h"
#include "brw_context.h"
-#include "brw_vs.h"
-#include "brw_gs.h"
-#include "brw_fs.h"
#include "brw_cfg.h"
+#include "brw_eu.h"
+#include "brw_fs.h"
#include "brw_nir.h"
-#include "glsl/ir_optimization.h"
-#include "glsl/glsl_parser_extras.h"
-#include "main/shaderapi.h"
-
-static void
-shader_debug_log_mesa(void *data, const char *fmt, ...)
-{
- struct brw_context *brw = (struct brw_context *)data;
- va_list args;
-
- va_start(args, fmt);
- GLuint msg_id = 0;
- _mesa_gl_vdebug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_OTHER,
- MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
- va_end(args);
-}
-
-static void
-shader_perf_log_mesa(void *data, const char *fmt, ...)
-{
- struct brw_context *brw = (struct brw_context *)data;
-
- va_list args;
- va_start(args, fmt);
-
- if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
- va_list args_copy;
- va_copy(args_copy, args);
- vfprintf(stderr, fmt, args_copy);
- va_end(args_copy);
- }
-
- if (brw->perf_debug) {
- GLuint msg_id = 0;
- _mesa_gl_vdebug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_PERFORMANCE,
- MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
- }
- va_end(args);
-}
-
-bool
-is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
-{
- switch (stage) {
- case MESA_SHADER_FRAGMENT:
- case MESA_SHADER_COMPUTE:
- return true;
- case MESA_SHADER_GEOMETRY:
- return compiler->scalar_gs;
- case MESA_SHADER_VERTEX:
- return compiler->scalar_vs;
- default:
- return false;
- }
-}
-
-struct brw_compiler *
-brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
-{
- struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
-
- compiler->devinfo = devinfo;
- compiler->shader_debug_log = shader_debug_log_mesa;
- compiler->shader_perf_log = shader_perf_log_mesa;
-
- brw_fs_alloc_reg_sets(compiler);
- brw_vec4_alloc_reg_set(compiler);
-
- if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
- compiler->scalar_vs = true;
-
- if (devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false))
- compiler->scalar_gs = true;
-
- nir_shader_compiler_options *nir_options =
- rzalloc(compiler, nir_shader_compiler_options);
- nir_options->native_integers = true;
- /* In order to help allow for better CSE at the NIR level we tell NIR
- * to split all ffma instructions during opt_algebraic and we then
- * re-combine them as a later step.
- */
- nir_options->lower_ffma = true;
- nir_options->lower_sub = true;
- /* In the vec4 backend, our dpN instruction replicates its result to all
- * the components of a vec4. We would like NIR to give us replicated fdot
- * instructions because it can optimize better for us.
- *
- * For the FS backend, it should be lowered away by the scalarizing pass so
- * we should never see fdot anyway.
- */
- nir_options->fdot_replicates = true;
-
- /* We want the GLSL compiler to emit code that uses condition codes */
- for (int i = 0; i < MESA_SHADER_STAGES; i++) {
- compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
- compiler->glsl_compiler_options[i].MaxIfDepth =
- devinfo->gen < 6 ? 16 : UINT_MAX;
-
- compiler->glsl_compiler_options[i].EmitCondCodes = true;
- compiler->glsl_compiler_options[i].EmitNoNoise = true;
- compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
- compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
- compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
- compiler->glsl_compiler_options[i].LowerClipDistance = true;
-
- bool is_scalar = is_scalar_shader_stage(compiler, i);
-
- compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
- compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
- compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
-
- /* !ARB_gpu_shader5 */
- if (devinfo->gen < 7)
- compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
-
- compiler->glsl_compiler_options[i].NirOptions = nir_options;
+#include "brw_vec4_tes.h"
+#include "main/uniforms.h"
- compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
- }
-
- return compiler;
-}
-
-struct gl_shader *
-brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
-{
- struct brw_shader *shader;
-
- shader = rzalloc(NULL, struct brw_shader);
- if (shader) {
- shader->base.Type = type;
- shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
- shader->base.Name = name;
- _mesa_init_shader(ctx, &shader->base);
- }
-
- return &shader->base;
-}
-
-void
+extern "C" void
brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
unsigned surf_index)
{
return BRW_REGISTER_TYPE_UD;
case GLSL_TYPE_IMAGE:
return BRW_REGISTER_TYPE_UD;
+ case GLSL_TYPE_DOUBLE:
+ return BRW_REGISTER_TYPE_DF;
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
- case GLSL_TYPE_DOUBLE:
+ case GLSL_TYPE_FUNCTION:
unreachable("not reached");
}
}
const char *
-brw_instruction_name(enum opcode op)
+brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
{
switch (op) {
case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
- assert(opcode_descs[op].name);
- return opcode_descs[op].name;
+ /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
+ * start of a loop in the IR.
+ */
+ if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
+ return "do";
+
+ assert(brw_opcode_desc(devinfo, op)->name);
+ return brw_opcode_desc(devinfo, op)->name;
case FS_OPCODE_FB_WRITE:
return "fb_write";
case FS_OPCODE_FB_WRITE_LOGICAL:
return "fb_write_logical";
- case FS_OPCODE_PACK_STENCIL_REF:
- return "pack_stencil_ref";
- case FS_OPCODE_BLORP_FB_WRITE:
- return "blorp_fb_write";
case FS_OPCODE_REP_FB_WRITE:
return "rep_fb_write";
+ case FS_OPCODE_FB_READ:
+ return "fb_read";
+ case FS_OPCODE_FB_READ_LOGICAL:
+ return "fb_read_logical";
case SHADER_OPCODE_RCP:
return "rcp";
return "txf";
case SHADER_OPCODE_TXF_LOGICAL:
return "txf_logical";
+ case SHADER_OPCODE_TXF_LZ:
+ return "txf_lz";
case SHADER_OPCODE_TXL:
return "txl";
case SHADER_OPCODE_TXL_LOGICAL:
return "txl_logical";
+ case SHADER_OPCODE_TXL_LZ:
+ return "txl_lz";
case SHADER_OPCODE_TXS:
return "txs";
case SHADER_OPCODE_TXS_LOGICAL:
return "tg4_offset_logical";
case SHADER_OPCODE_SAMPLEINFO:
return "sampleinfo";
+ case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
+ return "sampleinfo_logical";
case SHADER_OPCODE_SHADER_TIME_ADD:
return "shader_time_add";
case SHADER_OPCODE_LOAD_PAYLOAD:
return "load_payload";
+ case FS_OPCODE_PACK:
+ return "pack";
case SHADER_OPCODE_GEN4_SCRATCH_READ:
return "gen4_scratch_read";
return "gen8_urb_write_simd8_masked_per_slot";
case SHADER_OPCODE_URB_READ_SIMD8:
return "urb_read_simd8";
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
+ return "urb_read_simd8_per_slot";
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
return "find_live_channel";
return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
return "uniform_pull_const_gen7";
- case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
- return "varying_pull_const";
+ case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
+ return "varying_pull_const_gen4";
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
return "varying_pull_const_gen7";
+ case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
+ return "varying_pull_const_logical";
case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
return "mov_dispatch_to_flags";
case FS_OPCODE_PLACEHOLDER_HALT:
return "placeholder_halt";
- case FS_OPCODE_INTERPOLATE_AT_CENTROID:
- return "interp_centroid";
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
return "interp_sample";
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
return "barrier";
case SHADER_OPCODE_MULH:
return "mulh";
+ case SHADER_OPCODE_MOV_INDIRECT:
+ return "mov_indirect";
+
+ case VEC4_OPCODE_URB_READ:
+ return "urb_read";
+ case TCS_OPCODE_GET_INSTANCE_ID:
+ return "tcs_get_instance_id";
+ case TCS_OPCODE_URB_WRITE:
+ return "tcs_urb_write";
+ case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
+ return "tcs_set_input_urb_offsets";
+ case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
+ return "tcs_set_output_urb_offsets";
+ case TCS_OPCODE_GET_PRIMITIVE_ID:
+ return "tcs_get_primitive_id";
+ case TCS_OPCODE_CREATE_BARRIER_HEADER:
+ return "tcs_create_barrier_header";
+ case TCS_OPCODE_SRC0_010_IS_ZERO:
+ return "tcs_src0<0,1,0>_is_zero";
+ case TCS_OPCODE_RELEASE_INPUT:
+ return "tcs_release_input";
+ case TCS_OPCODE_THREAD_END:
+ return "tcs_thread_end";
+ case TES_OPCODE_CREATE_INPUT_READ_HEADER:
+ return "tes_create_input_read_header";
+ case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
+ return "tes_add_indirect_urb_offset";
+ case TES_OPCODE_GET_PRIMITIVE_ID:
+ return "tes_get_primitive_id";
}
unreachable("not reached");
unsigned ud;
int d;
float f;
- } imm = { reg->ud }, sat_imm = { 0 };
+ double df;
+ } imm, sat_imm = { 0 };
+
+ const unsigned size = type_sz(type);
+
+ /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
+ * irrelevant, so just check the size of the type and copy from/to an
+ * appropriately sized field.
+ */
+ if (size < 8)
+ imm.ud = reg->ud;
+ else
+ imm.df = reg->df;
switch (type) {
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UW:
+ case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
/* Nothing to do. */
return false;
- case BRW_REGISTER_TYPE_UW:
- sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
- break;
- case BRW_REGISTER_TYPE_W:
- sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
- break;
case BRW_REGISTER_TYPE_F:
sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
break;
+ case BRW_REGISTER_TYPE_DF:
+ sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
+ break;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_VF:
unreachable("unimplemented: saturate vector immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- unreachable("unimplemented: saturate DF/HF immediate");
+ unreachable("unimplemented: saturate HF immediate");
}
- if (imm.ud != sat_imm.ud) {
- reg->ud = sat_imm.ud;
- return true;
+ if (size < 8) {
+ if (imm.ud != sat_imm.ud) {
+ reg->ud = sat_imm.ud;
+ return true;
+ }
+ } else {
+ if (imm.df != sat_imm.df) {
+ reg->df = sat_imm.df;
+ return true;
+ }
}
return false;
}
case BRW_REGISTER_TYPE_VF:
reg->ud ^= 0x80808080;
return true;
+ case BRW_REGISTER_TYPE_DF:
+ reg->df = -reg->df;
+ return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
assert(!"unimplemented: negate UQ/Q immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- assert(!"unimplemented: negate DF/HF immediate");
+ assert(!"unimplemented: negate HF immediate");
}
return false;
case BRW_REGISTER_TYPE_F:
reg->f = fabsf(reg->f);
return true;
+ case BRW_REGISTER_TYPE_DF:
+ reg->df = fabs(reg->df);
+ return true;
case BRW_REGISTER_TYPE_VF:
reg->ud &= ~0x80808080;
return true;
assert(!"unimplemented: abs V immediate");
case BRW_REGISTER_TYPE_Q:
assert(!"unimplemented: abs Q immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- assert(!"unimplemented: abs DF/HF immediate");
+ assert(!"unimplemented: abs HF immediate");
}
return false;
}
+unsigned
+tesslevel_outer_components(GLenum tes_primitive_mode)
+{
+ switch (tes_primitive_mode) {
+ case GL_QUADS:
+ return 4;
+ case GL_TRIANGLES:
+ return 3;
+ case GL_ISOLINES:
+ return 2;
+ default:
+ unreachable("Bogus tessellation domain");
+ }
+ return 0;
+}
+
+unsigned
+tesslevel_inner_components(GLenum tes_primitive_mode)
+{
+ switch (tes_primitive_mode) {
+ case GL_QUADS:
+ return 2;
+ case GL_TRIANGLES:
+ return 1;
+ case GL_ISOLINES:
+ return 0;
+ default:
+ unreachable("Bogus tessellation domain");
+ }
+ return 0;
+}
+
+/**
+ * Given a normal .xyzw writemask, convert it to a writemask for a vector
+ * that's stored backwards, i.e. .wzyx.
+ */
+unsigned
+writemask_for_backwards_vector(unsigned mask)
+{
+ unsigned new_mask = 0;
+
+ for (int i = 0; i < 4; i++)
+ new_mask |= ((mask >> i) & 1) << (3 - i);
+
+ return new_mask;
+}
+
backend_shader::backend_shader(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
stage_name = _mesa_shader_stage_to_string(stage);
stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
+ is_passthrough_shader =
+ nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
+}
+
+bool
+backend_reg::equals(const backend_reg &r) const
+{
+ return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
}
bool
if (file != IMM)
return false;
- return d == 0;
+ switch (type) {
+ case BRW_REGISTER_TYPE_F:
+ return f == 0;
+ case BRW_REGISTER_TYPE_DF:
+ return df == 0;
+ case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UD:
+ return d == 0;
+ default:
+ return false;
+ }
}
bool
if (file != IMM)
return false;
- return type == BRW_REGISTER_TYPE_F
- ? f == 1.0
- : d == 1;
+ switch (type) {
+ case BRW_REGISTER_TYPE_F:
+ return f == 1.0f;
+ case BRW_REGISTER_TYPE_DF:
+ return df == 1.0;
+ case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UD:
+ return d == 1;
+ default:
+ return false;
+ }
}
bool
switch (type) {
case BRW_REGISTER_TYPE_F:
return f == -1.0;
+ case BRW_REGISTER_TYPE_DF:
+ return df == -1.0;
case BRW_REGISTER_TYPE_D:
return d == -1;
default:
bool
backend_reg::is_null() const
{
- return file == HW_REG &&
- brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE &&
- nr == BRW_ARF_NULL;
+ return file == ARF && nr == BRW_ARF_NULL;
}
bool
backend_reg::is_accumulator() const
{
- return file == HW_REG &&
- brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE &&
- nr == BRW_ARF_ACCUMULATOR;
+ return file == ARF && nr == BRW_ARF_ACCUMULATOR;
}
bool
}
bool
-backend_instruction::is_3src() const
+backend_instruction::is_3src(const struct brw_device_info *devinfo) const
{
- return ::is_3src(opcode);
+ return ::is_3src(devinfo, opcode);
}
bool
opcode == FS_OPCODE_TXB ||
opcode == SHADER_OPCODE_TXD ||
opcode == SHADER_OPCODE_TXF ||
+ opcode == SHADER_OPCODE_TXF_LZ ||
opcode == SHADER_OPCODE_TXF_CMS ||
opcode == SHADER_OPCODE_TXF_CMS_W ||
opcode == SHADER_OPCODE_TXF_UMS ||
opcode == SHADER_OPCODE_TXF_MCS ||
opcode == SHADER_OPCODE_TXL ||
+ opcode == SHADER_OPCODE_TXL_LZ ||
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD ||
opcode == SHADER_OPCODE_TG4 ||
- opcode == SHADER_OPCODE_TG4_OFFSET);
+ opcode == SHADER_OPCODE_TG4_OFFSET ||
+ opcode == SHADER_OPCODE_SAMPLEINFO);
}
bool
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
case FS_OPCODE_FB_WRITE:
+ case FS_OPCODE_FB_WRITE_LOGICAL:
case SHADER_OPCODE_BARRIER:
+ case TCS_OPCODE_URB_WRITE:
+ case TCS_OPCODE_RELEASE_INPUT:
return true;
default:
return false;
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_READ:
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
+ case SHADER_OPCODE_URB_READ_SIMD8:
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
+ case VEC4_OPCODE_URB_READ:
return true;
default:
return false;
adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
{
for (bblock_t *block_iter = start_block->next();
- !block_iter->link.is_tail_sentinel();
+ block_iter;
block_iter = block_iter->next()) {
block_iter->start_ip += ip_adjustment;
block_iter->end_ip += ip_adjustment;
void
backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
{
+ assert(this != inst);
+
if (!this->is_head_sentinel())
assert(inst_is_in_block(block, this) || !"Instruction not in block");
void
backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
{
+ assert(this != inst);
+
if (!this->is_tail_sentinel())
assert(inst_is_in_block(block, this) || !"Instruction not in block");
cfg = new(mem_ctx) cfg_t(&this->instructions);
}
-void
-backend_shader::invalidate_cfg()
-{
- ralloc_free(this->cfg);
- this->cfg = NULL;
-}
-
/**
* Sets up the starting offsets for the groups of binding table entries
* commong to all pipeline stages.
* unused but also make sure that addition of small offsets to them will
* trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
*/
-void
+uint32_t
brw_assign_common_binding_table_offsets(gl_shader_stage stage,
const struct brw_device_info *devinfo,
const struct gl_shader_program *shader_prog,
struct brw_stage_prog_data *stage_prog_data,
uint32_t next_binding_table_offset)
{
- const struct gl_shader *shader = NULL;
- int num_textures = _mesa_fls(prog->SamplersUsed);
+ const struct gl_linked_shader *shader = NULL;
+ int num_textures = util_last_bit(prog->SamplersUsed);
if (shader_prog)
shader = shader_prog->_LinkedShaders[stage];
stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
next_binding_table_offset++;
- assert(next_binding_table_offset <= BRW_MAX_SURFACES);
+ /* Plane 0 is just the regular texture section */
+ stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
+
+ stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
+
+ stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
+
+ assert(next_binding_table_offset <= BRW_MAX_SURFACES);
+ return next_binding_table_offset;
}
static void
}
}
+extern "C" const unsigned *
+brw_compile_tes(const struct brw_compiler *compiler,
+ void *log_data,
+ void *mem_ctx,
+ const struct brw_tes_prog_key *key,
+ struct brw_tes_prog_data *prog_data,
+ const nir_shader *src_shader,
+ struct gl_shader_program *shader_prog,
+ int shader_time_index,
+ unsigned *final_assembly_size,
+ char **error_str)
+{
+ const struct brw_device_info *devinfo = compiler->devinfo;
+ struct gl_linked_shader *shader =
+ shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
+ const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
+
+ nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
+ nir->info.inputs_read = key->inputs_read;
+ nir->info.patch_inputs_read = key->patch_inputs_read;
+
+ struct brw_vue_map input_vue_map;
+ brw_compute_tess_vue_map(&input_vue_map,
+ nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
+ nir->info.patch_inputs_read);
+
+ nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
+ brw_nir_lower_tes_inputs(nir, &input_vue_map);
+ brw_nir_lower_vue_outputs(nir, is_scalar);
+ nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
+
+ brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
+ nir->info.outputs_written,
+ nir->info.separate_shader);
+
+ unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
+
+ assert(output_size_bytes >= 1);
+ if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
+ if (error_str)
+ *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
+ return NULL;
+ }
+
+ /* URB entry sizes are stored as a multiple of 64 bytes. */
+ prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
+
+ bool need_patch_header = nir->info.system_values_read &
+ (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
+ BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
+
+ /* The TES will pull most inputs using URB read messages.
+ *
+ * However, we push the patch header for TessLevel factors when required,
+ * as it's a tiny amount of extra data.
+ */
+ prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
+
+ if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
+ fprintf(stderr, "TES Input ");
+ brw_print_vue_map(stderr, &input_vue_map);
+ fprintf(stderr, "TES Output ");
+ brw_print_vue_map(stderr, &prog_data->base.vue_map);
+ }
+
+ if (is_scalar) {
+ fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
+ &prog_data->base.base, shader->Program, nir, 8,
+ shader_time_index, &input_vue_map);
+ if (!v.run_tes()) {
+ if (error_str)
+ *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
+ return NULL;
+ }
+
+ prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
+ prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
+
+ fs_generator g(compiler, log_data, mem_ctx, (void *) key,
+ &prog_data->base.base, v.promoted_constants, false,
+ MESA_SHADER_TESS_EVAL);
+ if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
+ g.enable_debug(ralloc_asprintf(mem_ctx,
+ "%s tessellation evaluation shader %s",
+ nir->info.label ? nir->info.label
+ : "unnamed",
+ nir->info.name));
+ }
+
+ g.generate_code(v.cfg, 8);
+
+ return g.get_assembly(final_assembly_size);
+ } else {
+ brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
+ nir, mem_ctx, shader_time_index);
+ if (!v.run()) {
+ if (error_str)
+ *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
+ return NULL;
+ }
+
+ if (unlikely(INTEL_DEBUG & DEBUG_TES))
+ v.dump_instructions();
+
+ return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
+ &prog_data->base, v.cfg,
+ final_assembly_size);
+ }
+}