#include "brw_context.h"
}
#include "brw_vs.h"
-#include "brw_vec4_gs.h"
+#include "brw_gs.h"
#include "brw_fs.h"
+#include "brw_cfg.h"
#include "glsl/ir_optimization.h"
#include "glsl/glsl_parser_extras.h"
#include "main/shaderapi.h"
return &shader->base;
}
-struct gl_shader_program *
-brw_new_shader_program(struct gl_context *ctx, GLuint name)
-{
- struct gl_shader_program *prog = rzalloc(NULL, struct gl_shader_program);
- if (prog) {
- prog->Name = name;
- _mesa_init_shader_program(ctx, prog);
- }
- return prog;
-}
-
/**
* Performs a compile of the shader stages even when we don't know
* what non-orthogonal state will be set, in the hope that it reflects
* the eventual NOS used, and thus allows us to produce link failures.
*/
static bool
-brw_shader_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
+brw_shader_precompile(struct gl_context *ctx,
+ struct gl_shader_program *sh_prog)
{
- struct brw_context *brw = brw_context(ctx);
+ struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
+ struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
+ struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
- if (brw->precompile && !brw_fs_precompile(ctx, prog))
+ if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
return false;
- if (brw->precompile && !brw_gs_precompile(ctx, prog))
+ if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
return false;
- if (brw->precompile && !brw_vs_precompile(ctx, prog))
+ if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
return false;
return true;
}
+static inline bool
+is_scalar_shader_stage(struct brw_context *brw, int stage)
+{
+ switch (stage) {
+ case MESA_SHADER_FRAGMENT:
+ return true;
+ case MESA_SHADER_VERTEX:
+ return brw->scalar_vs;
+ default:
+ return false;
+ }
+}
+
static void
brw_lower_packing_builtins(struct brw_context *brw,
gl_shader_stage shader_type,
int ops = LOWER_PACK_SNORM_2x16
| LOWER_UNPACK_SNORM_2x16
| LOWER_PACK_UNORM_2x16
- | LOWER_UNPACK_UNORM_2x16
- | LOWER_PACK_SNORM_4x8
+ | LOWER_UNPACK_UNORM_2x16;
+
+ if (is_scalar_shader_stage(brw, shader_type)) {
+ ops |= LOWER_UNPACK_UNORM_4x8
| LOWER_UNPACK_SNORM_4x8
| LOWER_PACK_UNORM_4x8
- | LOWER_UNPACK_UNORM_4x8;
+ | LOWER_PACK_SNORM_4x8;
+ }
if (brw->gen >= 7) {
/* Gen7 introduced the f32to16 and f16to32 instructions, which can be
* lowering is needed. For SOA code, the Half2x16 ops must be
* scalarized.
*/
- if (shader_type == MESA_SHADER_FRAGMENT) {
+ if (is_scalar_shader_stage(brw, shader_type)) {
ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
| LOWER_UNPACK_HALF_2x16_TO_SPLIT;
}
unsigned int stage;
for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
+ const struct gl_shader_compiler_options *options =
+ &ctx->Const.ShaderCompilerOptions[stage];
struct brw_shader *shader =
(struct brw_shader *)shProg->_LinkedShaders[stage];
continue;
struct gl_program *prog =
- ctx->Driver.NewProgram(ctx, _mesa_program_index_to_target(stage),
+ ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
shader->base.Name);
if (!prog)
return false;
_mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
- void *mem_ctx = ralloc_context(NULL);
bool progress;
- if (shader->ir)
- ralloc_free(shader->ir);
- shader->ir = new(shader) exec_list;
- clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
-
/* lower_packing_builtins() inserts arithmetic instructions, so it
* must precede lower_instructions().
*/
- brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->ir);
- do_mat_op_to_vec(shader->ir);
+ brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->base.ir);
+ do_mat_op_to_vec(shader->base.ir);
const int bitfield_insert = brw->gen >= 7
? BITFIELD_INSERT_TO_BFM_BFI
: 0;
- const int lrp_to_arith = brw->gen < 6 ? LRP_TO_ARITH : 0;
- lower_instructions(shader->ir,
+ lower_instructions(shader->base.ir,
MOD_TO_FRACT |
DIV_TO_MUL_RCP |
SUB_TO_ADD_NEG |
EXP_TO_EXP2 |
LOG_TO_LOG2 |
bitfield_insert |
- lrp_to_arith |
LDEXP_TO_ARITH);
/* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
* if-statements need to be flattened.
*/
if (brw->gen < 6)
- lower_if_to_cond_assign(shader->ir, 16);
-
- do_lower_texture_projection(shader->ir);
- brw_lower_texture_gradients(brw, shader->ir);
- do_vec_index_to_cond_assign(shader->ir);
- lower_vector_insert(shader->ir, true);
- brw_do_cubemap_normalize(shader->ir);
- brw_do_lower_offset_arrays(shader->ir);
- brw_do_lower_unnormalized_offset(shader->ir);
- lower_noise(shader->ir);
- lower_quadop_vector(shader->ir, false);
-
- bool input = true;
- bool output = stage == MESA_SHADER_FRAGMENT;
- bool temp = stage == MESA_SHADER_FRAGMENT;
- bool uniform = false;
+ lower_if_to_cond_assign(shader->base.ir, 16);
+
+ do_lower_texture_projection(shader->base.ir);
+ brw_lower_texture_gradients(brw, shader->base.ir);
+ do_vec_index_to_cond_assign(shader->base.ir);
+ lower_vector_insert(shader->base.ir, true);
+ brw_do_cubemap_normalize(shader->base.ir);
+ lower_offset_arrays(shader->base.ir);
+ brw_do_lower_unnormalized_offset(shader->base.ir);
+ lower_noise(shader->base.ir);
+ lower_quadop_vector(shader->base.ir, false);
bool lowered_variable_indexing =
- lower_variable_index_to_cond_assign(shader->ir,
- input, output, temp, uniform);
+ lower_variable_index_to_cond_assign(shader->base.ir,
+ options->EmitNoIndirectInput,
+ options->EmitNoIndirectOutput,
+ options->EmitNoIndirectTemp,
+ options->EmitNoIndirectUniform);
if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
perf_debug("Unsupported form of variable indexing in FS; falling "
"back to very inefficient code generation\n");
}
- /* FINISHME: Do this before the variable index lowering. */
- lower_ubo_reference(&shader->base, shader->ir);
+ lower_ubo_reference(&shader->base, shader->base.ir);
do {
progress = false;
- if (stage == MESA_SHADER_FRAGMENT) {
- brw_do_channel_expressions(shader->ir);
- brw_do_vector_splitting(shader->ir);
+ if (is_scalar_shader_stage(brw, stage)) {
+ brw_do_channel_expressions(shader->base.ir);
+ brw_do_vector_splitting(shader->base.ir);
}
- progress = do_lower_jumps(shader->ir, true, true,
+ progress = do_lower_jumps(shader->base.ir, true, true,
true, /* main return */
false, /* continue */
false /* loops */
) || progress;
- progress = do_common_optimization(shader->ir, true, true, 32,
- &ctx->ShaderCompilerOptions[stage])
+ progress = do_common_optimization(shader->base.ir, true, true,
+ options, ctx->Const.NativeIntegers)
|| progress;
} while (progress);
* too late. At that point, the values for the built-in uniforms won't
* get sent to the shader.
*/
- foreach_list(node, shader->ir) {
- ir_variable *var = ((ir_instruction *) node)->as_variable();
+ foreach_in_list(ir_instruction, node, shader->base.ir) {
+ ir_variable *var = node->as_variable();
if ((var == NULL) || (var->data.mode != ir_var_uniform)
|| (strncmp(var->name, "gl_", 3) != 0))
continue;
- const ir_state_slot *const slots = var->state_slots;
- assert(var->state_slots != NULL);
+ const ir_state_slot *const slots = var->get_state_slots();
+ assert(slots != NULL);
- for (unsigned int i = 0; i < var->num_state_slots; i++) {
+ for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
_mesa_add_state_reference(prog->Parameters,
(gl_state_index *) slots[i].tokens);
}
}
- validate_ir_tree(shader->ir);
+ validate_ir_tree(shader->base.ir);
- reparent_ir(shader->ir, shader->ir);
- ralloc_free(mem_ctx);
-
- do_set_program_inouts(shader->ir, prog, shader->base.Stage);
+ do_set_program_inouts(shader->base.ir, prog, shader->base.Stage);
prog->SamplersUsed = shader->base.active_samplers;
+ prog->ShadowSamplers = shader->base.shadow_samplers;
_mesa_update_shader_textures_used(shProg, prog);
_mesa_reference_program(ctx, &shader->base.Program, prog);
brw_add_texrect_params(prog);
- /* This has to be done last. Any operation that can cause
- * prog->ParameterValues to get reallocated (e.g., anything that adds a
- * program constant) has to happen before creating this linkage.
- */
- _mesa_associate_uniform_storage(ctx, shProg, prog->Parameters);
-
_mesa_reference_program(ctx, &prog, NULL);
- if (ctx->Shader.Flags & GLSL_DUMP) {
- printf("\n");
- printf("GLSL IR for linked %s program %d:\n",
- _mesa_shader_stage_to_string(shader->base.Stage),
- shProg->Name);
- _mesa_print_ir(shader->base.ir, NULL);
- printf("\n");
+ if (ctx->_Shader->Flags & GLSL_DUMP) {
+ fprintf(stderr, "\n");
+ fprintf(stderr, "GLSL IR for linked %s program %d:\n",
+ _mesa_shader_stage_to_string(shader->base.Stage),
+ shProg->Name);
+ _mesa_print_ir(stderr, shader->base.ir, NULL);
+ fprintf(stderr, "\n");
}
}
- if (ctx->Shader.Flags & GLSL_DUMP) {
+ if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
for (unsigned i = 0; i < shProg->NumShaders; i++) {
const struct gl_shader *sh = shProg->Shaders[i];
if (!sh)
continue;
- printf("GLSL %s shader %d source for linked program %d:\n",
- _mesa_shader_stage_to_string(sh->Stage),
- i,
- shProg->Name);
- printf("%s", sh->Source);
- printf("\n");
+ fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
+ _mesa_shader_stage_to_string(sh->Stage),
+ i, shProg->Name);
+ fprintf(stderr, "%s", sh->Source);
+ fprintf(stderr, "\n");
}
}
- if (!brw_shader_precompile(ctx, shProg))
+ if (brw->precompile && !brw_shader_precompile(ctx, shProg))
return false;
return true;
}
-int
+enum brw_reg_type
brw_type_for_base_type(const struct glsl_type *type)
{
switch (type->base_type) {
* way to trip up if we don't.
*/
return BRW_REGISTER_TYPE_UD;
+ case GLSL_TYPE_IMAGE:
+ return BRW_REGISTER_TYPE_UD;
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
- assert(!"not reached");
- break;
+ unreachable("not reached");
}
return BRW_REGISTER_TYPE_F;
}
-uint32_t
+enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op)
{
switch (op) {
case ir_binop_any_nequal: /* same as nequal for scalars */
return BRW_CONDITIONAL_NZ;
default:
- assert(!"not reached: bad operation for comparison");
- return BRW_CONDITIONAL_NZ;
+ unreachable("not reached: bad operation for comparison");
}
}
case SHADER_OPCODE_INT_REMAINDER:
return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
default:
- assert(!"not reached: unknown math function");
- return 0;
+ unreachable("not reached: unknown math function");
}
}
uint32_t
-brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
+brw_texture_offset(struct gl_context *ctx, int *offsets,
+ unsigned num_components)
{
/* If the driver does not support GL_ARB_gpu_shader5, the offset
* must be constant.
*/
- assert(offset != NULL || ctx->Extensions.ARB_gpu_shader5);
-
- if (!offset) return 0; /* nonconstant offset; caller will handle it. */
+ assert(offsets != NULL || ctx->Extensions.ARB_gpu_shader5);
- signed char offsets[3];
- for (unsigned i = 0; i < offset->type->vector_elements; i++)
- offsets[i] = (signed char) offset->value.i[i];
+ if (!offsets) return 0; /* nonconstant offset; caller will handle it. */
/* Combine all three offsets into a single unsigned dword:
*
* bits 3:0 - R Offset (Z component)
*/
unsigned offset_bits = 0;
- for (unsigned i = 0; i < offset->type->vector_elements; i++) {
+ for (unsigned i = 0; i < num_components; i++) {
const unsigned shift = 4 * (2 - i);
offset_bits |= (offsets[i] << shift) & (0xF << shift);
}
const char *
brw_instruction_name(enum opcode op)
{
- char *fallback;
-
- if (op < ARRAY_SIZE(opcode_descs) && opcode_descs[op].name)
- return opcode_descs[op].name;
-
switch (op) {
+ case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
+ assert(opcode_descs[op].name);
+ return opcode_descs[op].name;
case FS_OPCODE_FB_WRITE:
return "fb_write";
+ case FS_OPCODE_BLORP_FB_WRITE:
+ return "blorp_fb_write";
+ case FS_OPCODE_REP_FB_WRITE:
+ return "rep_fb_write";
case SHADER_OPCODE_RCP:
return "rcp";
return "txs";
case FS_OPCODE_TXB:
return "txb";
- case SHADER_OPCODE_TXF_MS:
- return "txf_ms";
+ case SHADER_OPCODE_TXF_CMS:
+ return "txf_cms";
+ case SHADER_OPCODE_TXF_UMS:
+ return "txf_ums";
case SHADER_OPCODE_TXF_MCS:
return "txf_mcs";
+ case SHADER_OPCODE_LOD:
+ return "lod";
case SHADER_OPCODE_TG4:
return "tg4";
case SHADER_OPCODE_TG4_OFFSET:
return "tg4_offset";
+ case SHADER_OPCODE_SHADER_TIME_ADD:
+ return "shader_time_add";
+
+ case SHADER_OPCODE_UNTYPED_ATOMIC:
+ return "untyped_atomic";
+ case SHADER_OPCODE_UNTYPED_SURFACE_READ:
+ return "untyped_surface_read";
+
+ case SHADER_OPCODE_LOAD_PAYLOAD:
+ return "load_payload";
case SHADER_OPCODE_GEN4_SCRATCH_READ:
return "gen4_scratch_read";
return "gen4_scratch_write";
case SHADER_OPCODE_GEN7_SCRATCH_READ:
return "gen7_scratch_read";
-
- case FS_OPCODE_DDX:
- return "ddx";
- case FS_OPCODE_DDY:
- return "ddy";
+ case SHADER_OPCODE_URB_WRITE_SIMD8:
+ return "gen8_urb_write_simd8";
+
+ case VEC4_OPCODE_PACK_BYTES:
+ return "pack_bytes";
+ case VEC4_OPCODE_UNPACK_UNIFORM:
+ return "unpack_uniform";
+
+ case FS_OPCODE_DDX_COARSE:
+ return "ddx_coarse";
+ case FS_OPCODE_DDX_FINE:
+ return "ddx_fine";
+ case FS_OPCODE_DDY_COARSE:
+ return "ddy_coarse";
+ case FS_OPCODE_DDY_FINE:
+ return "ddy_fine";
case FS_OPCODE_PIXEL_X:
return "pixel_x";
case FS_OPCODE_DISCARD_JUMP:
return "discard_jump";
+ case FS_OPCODE_SET_OMASK:
+ return "set_omask";
+ case FS_OPCODE_SET_SAMPLE_ID:
+ return "set_sample_id";
case FS_OPCODE_SET_SIMD4X2_OFFSET:
return "set_simd4x2_offset";
case FS_OPCODE_PLACEHOLDER_HALT:
return "placeholder_halt";
+ case FS_OPCODE_INTERPOLATE_AT_CENTROID:
+ return "interp_centroid";
+ case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
+ return "interp_sample";
+ case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
+ return "interp_shared_offset";
+ case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
+ return "interp_per_slot_offset";
+
case VS_OPCODE_URB_WRITE:
return "vs_urb_write";
case VS_OPCODE_PULL_CONSTANT_LOAD:
case GS_OPCODE_URB_WRITE:
return "gs_urb_write";
+ case GS_OPCODE_URB_WRITE_ALLOCATE:
+ return "gs_urb_write_allocate";
case GS_OPCODE_THREAD_END:
return "gs_thread_end";
case GS_OPCODE_SET_WRITE_OFFSET:
return "set_write_offset";
case GS_OPCODE_SET_VERTEX_COUNT:
return "set_vertex_count";
- case GS_OPCODE_SET_DWORD_2_IMMED:
- return "set_dword_2_immed";
+ case GS_OPCODE_SET_DWORD_2:
+ return "set_dword_2";
case GS_OPCODE_PREPARE_CHANNEL_MASKS:
return "prepare_channel_masks";
case GS_OPCODE_SET_CHANNEL_MASKS:
return "set_channel_masks";
+ case GS_OPCODE_GET_INSTANCE_ID:
+ return "get_instance_id";
+ case GS_OPCODE_FF_SYNC:
+ return "ff_sync";
+ case GS_OPCODE_SET_PRIMITIVE_ID:
+ return "set_primitive_id";
+ case GS_OPCODE_SVB_WRITE:
+ return "gs_svb_write";
+ case GS_OPCODE_SVB_SET_DST_INDEX:
+ return "gs_svb_set_dst_index";
+ case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
+ return "gs_ff_sync_set_primitives";
+ }
- default:
- /* Yes, this leaks. It's in debug code, it should never occur, and if
- * it does, you should just add the case to the list above.
- */
- asprintf(&fallback, "op%d", op);
- return fallback;
+ unreachable("not reached");
+}
+
+bool
+brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
+{
+ union {
+ unsigned ud;
+ int d;
+ float f;
+ } imm = { reg->dw1.ud }, sat_imm;
+
+ switch (type) {
+ case BRW_REGISTER_TYPE_UD:
+ case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UQ:
+ case BRW_REGISTER_TYPE_Q:
+ /* Nothing to do. */
+ return false;
+ case BRW_REGISTER_TYPE_UW:
+ sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
+ break;
+ case BRW_REGISTER_TYPE_W:
+ sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
+ break;
+ case BRW_REGISTER_TYPE_F:
+ sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
+ break;
+ case BRW_REGISTER_TYPE_UB:
+ sat_imm.ud = CLAMP(imm.ud, 0, UCHAR_MAX);
+ break;
+ case BRW_REGISTER_TYPE_B:
+ sat_imm.d = CLAMP(imm.d, CHAR_MIN, CHAR_MAX);
+ break;
+ case BRW_REGISTER_TYPE_V:
+ case BRW_REGISTER_TYPE_UV:
+ case BRW_REGISTER_TYPE_VF:
+ assert(!"unimplemented: saturate vector immediate");
+ case BRW_REGISTER_TYPE_DF:
+ case BRW_REGISTER_TYPE_HF:
+ assert(!"unimplemented: saturate DF/HF immediate");
}
+
+ if (imm.ud != sat_imm.ud) {
+ reg->dw1.ud = sat_imm.ud;
+ return true;
+ }
+ return false;
+}
+
+backend_visitor::backend_visitor(struct brw_context *brw,
+ struct gl_shader_program *shader_prog,
+ struct gl_program *prog,
+ struct brw_stage_prog_data *stage_prog_data,
+ gl_shader_stage stage)
+ : brw(brw),
+ ctx(&brw->ctx),
+ shader(shader_prog ?
+ (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
+ shader_prog(shader_prog),
+ prog(prog),
+ stage_prog_data(stage_prog_data),
+ cfg(NULL),
+ stage(stage)
+{
+}
+
+bool
+backend_reg::is_zero() const
+{
+ if (file != IMM)
+ return false;
+
+ return fixed_hw_reg.dw1.d == 0;
+}
+
+bool
+backend_reg::is_one() const
+{
+ if (file != IMM)
+ return false;
+
+ return type == BRW_REGISTER_TYPE_F
+ ? fixed_hw_reg.dw1.f == 1.0
+ : fixed_hw_reg.dw1.d == 1;
+}
+
+bool
+backend_reg::is_null() const
+{
+ return file == HW_REG &&
+ fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ fixed_hw_reg.nr == BRW_ARF_NULL;
+}
+
+
+bool
+backend_reg::is_accumulator() const
+{
+ return file == HW_REG &&
+ fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
}
bool
-backend_instruction::is_tex()
+backend_instruction::is_3src() const
+{
+ return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
+}
+
+bool
+backend_instruction::is_tex() const
{
return (opcode == SHADER_OPCODE_TEX ||
opcode == FS_OPCODE_TXB ||
opcode == SHADER_OPCODE_TXD ||
opcode == SHADER_OPCODE_TXF ||
- opcode == SHADER_OPCODE_TXF_MS ||
+ opcode == SHADER_OPCODE_TXF_CMS ||
+ opcode == SHADER_OPCODE_TXF_UMS ||
opcode == SHADER_OPCODE_TXF_MCS ||
opcode == SHADER_OPCODE_TXL ||
opcode == SHADER_OPCODE_TXS ||
}
bool
-backend_instruction::is_math()
+backend_instruction::is_math() const
{
return (opcode == SHADER_OPCODE_RCP ||
opcode == SHADER_OPCODE_RSQ ||
}
bool
-backend_instruction::is_control_flow()
+backend_instruction::is_control_flow() const
{
switch (opcode) {
case BRW_OPCODE_DO:
}
bool
-backend_instruction::can_do_source_mods()
+backend_instruction::can_do_source_mods() const
{
switch (opcode) {
case BRW_OPCODE_ADDC:
}
}
+bool
+backend_instruction::can_do_saturate() const
+{
+ switch (opcode) {
+ case BRW_OPCODE_ADD:
+ case BRW_OPCODE_ASR:
+ case BRW_OPCODE_AVG:
+ case BRW_OPCODE_DP2:
+ case BRW_OPCODE_DP3:
+ case BRW_OPCODE_DP4:
+ case BRW_OPCODE_DPH:
+ case BRW_OPCODE_F16TO32:
+ case BRW_OPCODE_F32TO16:
+ case BRW_OPCODE_LINE:
+ case BRW_OPCODE_LRP:
+ case BRW_OPCODE_MAC:
+ case BRW_OPCODE_MACH:
+ case BRW_OPCODE_MAD:
+ case BRW_OPCODE_MATH:
+ case BRW_OPCODE_MOV:
+ case BRW_OPCODE_MUL:
+ case BRW_OPCODE_PLN:
+ case BRW_OPCODE_RNDD:
+ case BRW_OPCODE_RNDE:
+ case BRW_OPCODE_RNDU:
+ case BRW_OPCODE_RNDZ:
+ case BRW_OPCODE_SEL:
+ case BRW_OPCODE_SHL:
+ case BRW_OPCODE_SHR:
+ case FS_OPCODE_LINTERP:
+ case SHADER_OPCODE_COS:
+ case SHADER_OPCODE_EXP2:
+ case SHADER_OPCODE_LOG2:
+ case SHADER_OPCODE_POW:
+ case SHADER_OPCODE_RCP:
+ case SHADER_OPCODE_RSQ:
+ case SHADER_OPCODE_SIN:
+ case SHADER_OPCODE_SQRT:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool
+backend_instruction::can_do_cmod() const
+{
+ switch (opcode) {
+ case BRW_OPCODE_ADD:
+ case BRW_OPCODE_ADDC:
+ case BRW_OPCODE_AND:
+ case BRW_OPCODE_ASR:
+ case BRW_OPCODE_AVG:
+ case BRW_OPCODE_CMP:
+ case BRW_OPCODE_CMPN:
+ case BRW_OPCODE_DP2:
+ case BRW_OPCODE_DP3:
+ case BRW_OPCODE_DP4:
+ case BRW_OPCODE_DPH:
+ case BRW_OPCODE_F16TO32:
+ case BRW_OPCODE_F32TO16:
+ case BRW_OPCODE_FRC:
+ case BRW_OPCODE_LINE:
+ case BRW_OPCODE_LRP:
+ case BRW_OPCODE_LZD:
+ case BRW_OPCODE_MAC:
+ case BRW_OPCODE_MACH:
+ case BRW_OPCODE_MAD:
+ case BRW_OPCODE_MOV:
+ case BRW_OPCODE_MUL:
+ case BRW_OPCODE_NOT:
+ case BRW_OPCODE_OR:
+ case BRW_OPCODE_PLN:
+ case BRW_OPCODE_RNDD:
+ case BRW_OPCODE_RNDE:
+ case BRW_OPCODE_RNDU:
+ case BRW_OPCODE_RNDZ:
+ case BRW_OPCODE_SAD2:
+ case BRW_OPCODE_SADA2:
+ case BRW_OPCODE_SHL:
+ case BRW_OPCODE_SHR:
+ case BRW_OPCODE_SUBB:
+ case BRW_OPCODE_XOR:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool
+backend_instruction::reads_accumulator_implicitly() const
+{
+ switch (opcode) {
+ case BRW_OPCODE_MAC:
+ case BRW_OPCODE_MACH:
+ case BRW_OPCODE_SADA2:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool
+backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
+{
+ return writes_accumulator ||
+ (brw->gen < 6 &&
+ ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
+ (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
+ opcode != FS_OPCODE_CINTERP)));
+}
+
bool
backend_instruction::has_side_effects() const
{
switch (opcode) {
case SHADER_OPCODE_UNTYPED_ATOMIC:
+ case SHADER_OPCODE_URB_WRITE_SIMD8:
+ case FS_OPCODE_FB_WRITE:
return true;
default:
return false;
}
}
+#ifndef NDEBUG
+static bool
+inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
+{
+ bool found = false;
+ foreach_inst_in_block (backend_instruction, i, block) {
+ if (inst == i) {
+ found = true;
+ }
+ }
+ return found;
+}
+#endif
+
+static void
+adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
+{
+ for (bblock_t *block_iter = start_block->next();
+ !block_iter->link.is_tail_sentinel();
+ block_iter = block_iter->next()) {
+ block_iter->start_ip += ip_adjustment;
+ block_iter->end_ip += ip_adjustment;
+ }
+}
+
+void
+backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
+{
+ assert(inst_is_in_block(block, this) || !"Instruction not in block");
+
+ block->end_ip++;
+
+ adjust_later_block_ips(block, 1);
+
+ exec_node::insert_after(inst);
+}
+
+void
+backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
+{
+ assert(inst_is_in_block(block, this) || !"Instruction not in block");
+
+ block->end_ip++;
+
+ adjust_later_block_ips(block, 1);
+
+ exec_node::insert_before(inst);
+}
+
+void
+backend_instruction::insert_before(bblock_t *block, exec_list *list)
+{
+ assert(inst_is_in_block(block, this) || !"Instruction not in block");
+
+ unsigned num_inst = list->length();
+
+ block->end_ip += num_inst;
+
+ adjust_later_block_ips(block, num_inst);
+
+ exec_node::insert_before(list);
+}
+
+void
+backend_instruction::remove(bblock_t *block)
+{
+ assert(inst_is_in_block(block, this) || !"Instruction not in block");
+
+ adjust_later_block_ips(block, -1);
+
+ if (block->start_ip == block->end_ip) {
+ block->cfg->remove_block(block);
+ } else {
+ block->end_ip--;
+ }
+
+ exec_node::remove();
+}
+
void
backend_visitor::dump_instructions()
{
+ dump_instructions(NULL);
+}
+
+void
+backend_visitor::dump_instructions(const char *name)
+{
+ FILE *file = stderr;
+ if (name && geteuid() != 0) {
+ file = fopen(name, "w");
+ if (!file)
+ file = stderr;
+ }
+
int ip = 0;
- foreach_list(node, &this->instructions) {
- backend_instruction *inst = (backend_instruction *)node;
- printf("%d: ", ip++);
- dump_instruction(inst);
+ foreach_block_and_inst(block, backend_instruction, inst, cfg) {
+ if (!name)
+ fprintf(stderr, "%d: ", ip++);
+ dump_instruction(inst, file);
+ }
+
+ if (file != stderr) {
+ fclose(file);
}
}
+void
+backend_visitor::calculate_cfg()
+{
+ if (this->cfg)
+ return;
+ cfg = new(mem_ctx) cfg_t(&this->instructions);
+}
+
+void
+backend_visitor::invalidate_cfg()
+{
+ ralloc_free(this->cfg);
+ this->cfg = NULL;
+}
/**
* Sets up the starting offsets for the groups of binding table entries
}
if (prog->UsesGather) {
- stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
- next_binding_table_offset += num_textures;
+ if (brw->gen >= 8) {
+ stage_prog_data->binding_table.gather_texture_start =
+ stage_prog_data->binding_table.texture_start;
+ } else {
+ stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
+ }
} else {
stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
}
assert(next_binding_table_offset <= BRW_MAX_SURFACES);
- /* prog_data->base.binding_table.size will be set by mark_surface_used. */
+ /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
}
projects / mesa.git / blobdiff