return BRW_REGISTER_TYPE_UD;
case GLSL_TYPE_IMAGE:
return BRW_REGISTER_TYPE_UD;
+ case GLSL_TYPE_DOUBLE:
+ return BRW_REGISTER_TYPE_DF;
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
- case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_FUNCTION:
unreachable("not reached");
}
}
const char *
-brw_instruction_name(enum opcode op)
+brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
{
switch (op) {
case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
- assert(opcode_descs[op].name);
- return opcode_descs[op].name;
+ /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
+ * start of a loop in the IR.
+ */
+ if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
+ return "do";
+
+ assert(brw_opcode_desc(devinfo, op)->name);
+ return brw_opcode_desc(devinfo, op)->name;
case FS_OPCODE_FB_WRITE:
return "fb_write";
case FS_OPCODE_FB_WRITE_LOGICAL:
case SHADER_OPCODE_LOAD_PAYLOAD:
return "load_payload";
+ case FS_OPCODE_PACK:
+ return "pack";
case SHADER_OPCODE_GEN4_SCRATCH_READ:
return "gen4_scratch_read";
unsigned ud;
int d;
float f;
- } imm = { reg->ud }, sat_imm = { 0 };
+ double df;
+ } imm, sat_imm = { 0 };
+
+ const unsigned size = type_sz(type);
+
+ /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
+ * irrelevant, so just check the size of the type and copy from/to an
+ * appropriately sized field.
+ */
+ if (size < 8)
+ imm.ud = reg->ud;
+ else
+ imm.df = reg->df;
switch (type) {
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_F:
sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
break;
+ case BRW_REGISTER_TYPE_DF:
+ sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
+ break;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_VF:
unreachable("unimplemented: saturate vector immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- unreachable("unimplemented: saturate DF/HF immediate");
+ unreachable("unimplemented: saturate HF immediate");
}
- if (imm.ud != sat_imm.ud) {
- reg->ud = sat_imm.ud;
- return true;
+ if (size < 8) {
+ if (imm.ud != sat_imm.ud) {
+ reg->ud = sat_imm.ud;
+ return true;
+ }
+ } else {
+ if (imm.df != sat_imm.df) {
+ reg->df = sat_imm.df;
+ return true;
+ }
}
return false;
}
case BRW_REGISTER_TYPE_VF:
reg->ud ^= 0x80808080;
return true;
+ case BRW_REGISTER_TYPE_DF:
+ reg->df = -reg->df;
+ return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
unreachable("no UB/B immediates");
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
assert(!"unimplemented: negate UQ/Q immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- assert(!"unimplemented: negate DF/HF immediate");
+ assert(!"unimplemented: negate HF immediate");
}
return false;
case BRW_REGISTER_TYPE_F:
reg->f = fabsf(reg->f);
return true;
+ case BRW_REGISTER_TYPE_DF:
+ reg->df = fabs(reg->df);
+ return true;
case BRW_REGISTER_TYPE_VF:
reg->ud &= ~0x80808080;
return true;
assert(!"unimplemented: abs V immediate");
case BRW_REGISTER_TYPE_Q:
assert(!"unimplemented: abs Q immediate");
- case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_HF:
- assert(!"unimplemented: abs DF/HF immediate");
+ assert(!"unimplemented: abs HF immediate");
}
return false;
}
+unsigned
+tesslevel_outer_components(GLenum tes_primitive_mode)
+{
+ switch (tes_primitive_mode) {
+ case GL_QUADS:
+ return 4;
+ case GL_TRIANGLES:
+ return 3;
+ case GL_ISOLINES:
+ return 2;
+ default:
+ unreachable("Bogus tessellation domain");
+ }
+ return 0;
+}
+
+unsigned
+tesslevel_inner_components(GLenum tes_primitive_mode)
+{
+ switch (tes_primitive_mode) {
+ case GL_QUADS:
+ return 2;
+ case GL_TRIANGLES:
+ return 1;
+ case GL_ISOLINES:
+ return 0;
+ default:
+ unreachable("Bogus tessellation domain");
+ }
+ return 0;
+}
+
+/**
+ * Given a normal .xyzw writemask, convert it to a writemask for a vector
+ * that's stored backwards, i.e. .wzyx.
+ */
+unsigned
+writemask_for_backwards_vector(unsigned mask)
+{
+ unsigned new_mask = 0;
+
+ for (int i = 0; i < 4; i++)
+ new_mask |= ((mask >> i) & 1) << (3 - i);
+
+ return new_mask;
+}
+
backend_shader::backend_shader(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
stage_name = _mesa_shader_stage_to_string(stage);
stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
+ is_passthrough_shader =
+ nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
}
bool
backend_reg::equals(const backend_reg &r) const
{
- return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
- reg_offset == r.reg_offset;
+ return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
}
bool
if (file != IMM)
return false;
- return d == 0;
+ switch (type) {
+ case BRW_REGISTER_TYPE_F:
+ return f == 0;
+ case BRW_REGISTER_TYPE_DF:
+ return df == 0;
+ case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UD:
+ return d == 0;
+ default:
+ return false;
+ }
}
bool
if (file != IMM)
return false;
- return type == BRW_REGISTER_TYPE_F
- ? f == 1.0
- : d == 1;
+ switch (type) {
+ case BRW_REGISTER_TYPE_F:
+ return f == 1.0f;
+ case BRW_REGISTER_TYPE_DF:
+ return df == 1.0;
+ case BRW_REGISTER_TYPE_D:
+ case BRW_REGISTER_TYPE_UD:
+ return d == 1;
+ default:
+ return false;
+ }
}
bool
switch (type) {
case BRW_REGISTER_TYPE_F:
return f == -1.0;
+ case BRW_REGISTER_TYPE_DF:
+ return df == -1.0;
case BRW_REGISTER_TYPE_D:
return d == -1;
default:
}
bool
-backend_instruction::is_3src() const
+backend_instruction::is_3src(const struct brw_device_info *devinfo) const
{
- return ::is_3src(opcode);
+ return ::is_3src(devinfo, opcode);
}
bool
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD ||
opcode == SHADER_OPCODE_TG4 ||
- opcode == SHADER_OPCODE_TG4_OFFSET);
+ opcode == SHADER_OPCODE_TG4_OFFSET ||
+ opcode == SHADER_OPCODE_SAMPLEINFO);
}
bool
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_READ:
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
+ case SHADER_OPCODE_URB_READ_SIMD8:
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
+ case VEC4_OPCODE_URB_READ:
return true;
default:
return false;