intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.h

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 1054d7a589e42b0c39522609662482b921dd6b74..55769ff2e39ebd182cdb896a5ed64c3ebf334343 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -23,9 +23,61 @@
 
 #include <stdint.h>
 #include "brw_defines.h"
+#include "glsl/ir.h"
 
 #pragma once
 
+enum register_file {
+   BAD_FILE,
+   ARF,
+   GRF,
+   MRF,
+   IMM,
+   HW_REG, /* a struct brw_reg */
+   ATTR,
+   UNIFORM, /* prog_data->params[reg] */
+};
+
+#ifdef __cplusplus
+
+class backend_instruction : public exec_node {
+public:
+   bool is_tex();
+   bool is_math();
+   bool is_control_flow();
+
+   enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
+
+   uint32_t predicate;
+   bool predicate_inverse;
+};
+
+class backend_visitor : public ir_visitor {
+public:
+
+   struct brw_context *brw;
+   struct gl_context *ctx;
+   struct brw_shader *shader;
+   struct gl_shader_program *shader_prog;
+
+   /** ralloc context for temporary data used during compile */
+   void *mem_ctx;
+
+   /**
+    * List of either fs_inst or vec4_instruction (inheriting from
+    * backend_instruction)
+    */
+   exec_list instructions;
+
+   virtual void dump_instruction(backend_instruction *inst) = 0;
+   void dump_instructions();
+};
+
+uint32_t brw_texture_offset(ir_constant *offset);
+
+#endif /* __cplusplus */
+
 int brw_type_for_base_type(const struct glsl_type *type);
 uint32_t brw_conditional_for_comparison(unsigned int op);
 uint32_t brw_math_function(enum opcode op);
+const char *brw_instruction_name(enum opcode op);