i965/vec4: Make with_writemask() non-static.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.h

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 9d21d8f5eb8ebf476db5535af103c92165d2b857..55769ff2e39ebd182cdb896a5ed64c3ebf334343 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -27,8 +27,25 @@
 
 #pragma once
 
+enum register_file {
+   BAD_FILE,
+   ARF,
+   GRF,
+   MRF,
+   IMM,
+   HW_REG, /* a struct brw_reg */
+   ATTR,
+   UNIFORM, /* prog_data->params[reg] */
+};
+
+#ifdef __cplusplus
+
 class backend_instruction : public exec_node {
 public:
+   bool is_tex();
+   bool is_math();
+   bool is_control_flow();
+
    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 
    uint32_t predicate;
@@ -39,10 +56,9 @@ class backend_visitor : public ir_visitor {
 public:
 
    struct brw_context *brw;
-   struct intel_context *intel;
    struct gl_context *ctx;
    struct brw_shader *shader;
-   struct gl_shader_program *prog;
+   struct gl_shader_program *shader_prog;
 
    /** ralloc context for temporary data used during compile */
    void *mem_ctx;
@@ -52,10 +68,16 @@ public:
     * backend_instruction)
     */
    exec_list instructions;
+
+   virtual void dump_instruction(backend_instruction *inst) = 0;
+   void dump_instructions();
 };
 
+uint32_t brw_texture_offset(ir_constant *offset);
+
+#endif /* __cplusplus */
+
 int brw_type_for_base_type(const struct glsl_type *type);
 uint32_t brw_conditional_for_comparison(unsigned int op);
 uint32_t brw_math_function(enum opcode op);
-uint32_t brw_texture_offset(ir_constant *offset);
 const char *brw_instruction_name(enum opcode op);