i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.h

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index ac4df738009e52dad970d60b416b6386a5abdb44..925072f1349def7ede3ffea82c602d6cfd38bb18 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -26,6 +26,7 @@
 #include "brw_defines.h"
 #include "main/compiler.h"
 #include "glsl/ir.h"
+#include "program/prog_parameter.h"
 
 #ifdef __cplusplus
 #include "brw_ir_allocator.h"
@@ -220,7 +221,8 @@ enum instruction_scheduler_mode {
 class backend_shader {
 protected:
 
-   backend_shader(struct brw_context *brw,
+   backend_shader(const struct brw_compiler *compiler,
+                  void *log_data,
                   void *mem_ctx,
                   struct gl_shader_program *shader_prog,
                   struct gl_program *prog,
@@ -229,9 +231,10 @@ protected:
 
 public:
 
-   struct brw_context * const brw;
+   const struct brw_compiler *compiler;
+   void *log_data; /* Passed to compiler->*_log functions */
+
    const struct brw_device_info * const devinfo;
-   struct gl_context * const ctx;
    struct brw_shader * const shader;
    struct gl_shader_program * const shader_prog;
    struct gl_program * const prog;
@@ -266,6 +269,9 @@ public:
    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 
    virtual void invalidate_live_intervals() = 0;
+
+   virtual void setup_vector_uniform_values(const gl_constant_value *values,
+                                            unsigned n) = 0;
 };
 
 uint32_t brw_texture_offset(int *offsets, unsigned num_components);