i965: Refactor SIMD16-to-2xSIMD8 checks.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.h

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index f0d4f857cf1a52ddd75a23de212c66dc906e2d8c..f8cc98afd911c1a416535b059eec42f4809a2485 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -27,8 +27,15 @@
 #include "main/compiler.h"
 #include "glsl/ir.h"
 
+#ifdef __cplusplus
+#include "brw_ir_allocator.h"
+#endif
+
 #pragma once
 
+#define MAX_SAMPLER_MESSAGE_SIZE 11
+#define MAX_VGRF_SIZE 16
+
 enum PACKED register_file {
    BAD_FILE,
    GRF,
@@ -44,6 +51,7 @@ struct backend_reg
 #ifdef __cplusplus
    bool is_zero() const;
    bool is_one() const;
+   bool is_negative_one() const;
    bool is_null() const;
    bool is_accumulator() const;
 #endif
@@ -82,11 +90,14 @@ struct bblock_t;
 
 #ifdef __cplusplus
 struct backend_instruction : public exec_node {
+   bool is_3src() const;
    bool is_tex() const;
    bool is_math() const;
    bool is_control_flow() const;
+   bool is_commutative() const;
    bool can_do_source_mods() const;
    bool can_do_saturate() const;
+   bool can_do_cmod() const;
    bool reads_accumulator_implicitly() const;
    bool writes_accumulator_implicitly(struct brw_context *brw) const;
 
@@ -112,11 +123,11 @@ struct backend_instruction {
    const char *annotation;
    /** @} */
 
-   uint32_t texture_offset; /**< Texture offset bitfield */
-   uint32_t offset; /**< spill/unspill offset */
+   uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
    uint8_t mlen; /**< SEND message length */
    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
    uint8_t target; /**< MRT target. */
+   uint8_t regs_written; /**< Number of registers written by the instruction. */
 
    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
@@ -127,6 +138,13 @@ struct backend_instruction {
    bool no_dd_clear:1;
    bool no_dd_check:1;
    bool saturate:1;
+   bool shadow_compare:1;
+   bool header_present:1;
+
+   /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
+    * mod and predication.
+    */
+   unsigned flag_subreg:1;
 };
 
 #ifdef __cplusplus
@@ -168,6 +186,11 @@ public:
    cfg_t *cfg;
 
    gl_shader_stage stage;
+   bool debug_enabled;
+   const char *stage_name;
+   const char *stage_abbrev;
+
+   brw::simple_allocator alloc;
 
    virtual void dump_instruction(backend_instruction *inst) = 0;
    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
@@ -182,7 +205,8 @@ public:
    virtual void invalidate_live_intervals() = 0;
 };
 
-uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
+uint32_t brw_texture_offset(struct gl_context *ctx, int *offsets,
+                            unsigned num_components);
 
 #endif /* __cplusplus */
 
@@ -190,3 +214,24 @@ enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 uint32_t brw_math_function(enum opcode op);
 const char *brw_instruction_name(enum opcode op);
+bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
+bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
+bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+bool brw_vs_precompile(struct gl_context *ctx,
+                       struct gl_shader_program *shader_prog,
+                       struct gl_program *prog);
+bool brw_gs_precompile(struct gl_context *ctx,
+                       struct gl_shader_program *shader_prog,
+                       struct gl_program *prog);
+bool brw_fs_precompile(struct gl_context *ctx,
+                       struct gl_shader_program *shader_prog,
+                       struct gl_program *prog);
+
+#ifdef __cplusplus
+}
+#endif