/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
Permission is hereby granted, free of charge, to any person obtaining
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
extern const struct brw_tracked_state gen6_color_calc_state;
extern const struct brw_tracked_state gen6_depth_stencil_state;
extern const struct brw_tracked_state gen6_gs_state;
+extern const struct brw_tracked_state gen6_gs_push_constants;
extern const struct brw_tracked_state gen6_gs_binding_table;
extern const struct brw_tracked_state gen6_multisample_state;
extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
extern const struct brw_tracked_state gen6_wm_push_constants;
extern const struct brw_tracked_state gen6_wm_state;
extern const struct brw_tracked_state gen7_depthbuffer;
-extern const struct brw_tracked_state gen7_cc_viewport_state_pointer;
extern const struct brw_tracked_state gen7_clip_state;
extern const struct brw_tracked_state gen7_disable_stages;
extern const struct brw_tracked_state gen7_gs_push_constants;
extern const struct brw_tracked_state gen7_vs_state;
extern const struct brw_tracked_state gen7_wm_state;
extern const struct brw_tracked_state haswell_cut_index;
-
+extern const struct brw_tracked_state gen8_blend_state;
+extern const struct brw_tracked_state gen8_disable_stages;
+extern const struct brw_tracked_state gen8_gs_state;
+extern const struct brw_tracked_state gen8_index_buffer;
+extern const struct brw_tracked_state gen8_multisample_state;
+extern const struct brw_tracked_state gen8_pma_fix;
+extern const struct brw_tracked_state gen8_ps_blend;
+extern const struct brw_tracked_state gen8_ps_extra;
+extern const struct brw_tracked_state gen8_ps_state;
+extern const struct brw_tracked_state gen8_wm_depth_stencil;
+extern const struct brw_tracked_state gen8_wm_state;
+extern const struct brw_tracked_state gen8_raster_state;
+extern const struct brw_tracked_state gen8_sbe_state;
+extern const struct brw_tracked_state gen8_sf_state;
+extern const struct brw_tracked_state gen8_state_base_address;
+extern const struct brw_tracked_state gen8_sol_state;
+extern const struct brw_tracked_state gen8_sf_clip_viewport;
+extern const struct brw_tracked_state gen8_vertices;
+extern const struct brw_tracked_state gen8_vf_topology;
+extern const struct brw_tracked_state gen8_vs_state;
+
+static inline bool
+brw_state_dirty(struct brw_context *brw, GLuint mesa_flags, uint64_t brw_flags)
+{
+ return ((brw->state.dirty.mesa & mesa_flags) |
+ (brw->state.dirty.brw & brw_flags)) != 0;
+}
/* brw_misc_state.c */
void brw_upload_invariant_state(struct brw_context *brw);
* brw_state.c
*/
void brw_upload_state(struct brw_context *brw);
+void brw_clear_dirty_bits(struct brw_context *brw);
void brw_init_state(struct brw_context *brw);
void brw_destroy_state(struct brw_context *brw);
intel_batchbuffer_data(brw, (s), sizeof(*(s)), RENDER_RING)
void *brw_state_batch(struct brw_context *brw,
- enum state_struct_type type,
+ enum aub_state_struct_type type,
int size,
int alignment,
uint32_t *out_offset);
uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
-uint32_t brw_format_for_mesa_format(gl_format mesa_format);
+void brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
+ bool is_render_target,
+ unsigned *width, unsigned *height,
+ unsigned *pitch, uint32_t *tiling,
+ unsigned *format);
+
+uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
GLuint translate_tex_target(GLenum target);
GLuint translate_tex_format(struct brw_context *brw,
- gl_format mesa_format,
- GLenum depth_mode,
+ mesa_format mesa_format,
GLenum srgb_decode);
int brw_get_texture_swizzle(const struct gl_context *ctx,
const struct gl_texture_object *t);
/* gen7_wm_surface_state.c */
-unsigned brw_swizzle_to_scs(GLenum swizzle, bool need_green_to_blue);
uint32_t gen7_surface_tiling_mode(uint32_t tiling);
uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout l);
void gen7_set_surface_mcs_info(struct brw_context *brw,
void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
const struct brw_vue_map *vue_map);
-/* brw_wm_sampler_state.c */
-uint32_t translate_wrap_mode(GLenum wrap, bool using_nearest);
-void upload_default_color(struct brw_context *brw,
- struct gl_sampler_object *sampler,
- int unit,
- uint32_t *sdc_offset);
-void gen4_init_vtable_sampler_functions(struct brw_context *brw);
-
-/* gen7_sampler_state.c */
-void gen7_init_vtable_sampler_functions(struct brw_context *brw);
+/* gen8_surface_state.c */
+void gen8_init_vtable_surface_functions(struct brw_context *brw);
+
+/* brw_sampler_state.c */
+void brw_emit_sampler_state(struct brw_context *brw,
+ uint32_t *sampler_state,
+ uint32_t batch_offset_for_sampler_state,
+ unsigned min_filter,
+ unsigned mag_filter,
+ unsigned mip_filter,
+ unsigned max_anisotropy,
+ unsigned address_rounding,
+ unsigned wrap_s,
+ unsigned wrap_t,
+ unsigned wrap_r,
+ unsigned min_lod,
+ unsigned max_lod,
+ int lod_bias,
+ unsigned base_level,
+ unsigned shadow_function,
+ bool non_normalized_coordinates,
+ uint32_t border_color_offset);
/* gen6_sf_state.c */
void
uint32_t *flat_enables,
uint32_t *urb_entry_read_length);
+/* gen6_surface_state.c */
+void gen6_init_vtable_surface_functions(struct brw_context *brw);
+
/* brw_vs_surface_state.c */
void
-brw_upload_vec4_pull_constants(struct brw_context *brw,
- GLbitfield brw_new_constbuf,
- const struct gl_program *prog,
- struct brw_stage_state *stage_state,
- const struct brw_vec4_prog_data *prog_data);
+brw_upload_pull_constants(struct brw_context *brw,
+ GLbitfield brw_new_constbuf,
+ const struct gl_program *prog,
+ struct brw_stage_state *stage_state,
+ const struct brw_stage_prog_data *prog_data,
+ bool dword_pitch);
/* gen7_vs_state.c */
void