i965/miptree: Replace is_lossless_compressed with mt->aux_usage checks

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_batch.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 5a983c3d8477a6734a8f6e00a42cf9853494a7d9..5b6f3af93d86c87c29d87053c3542d266524a11d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -1,8 +1,8 @@
 /*
  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
  develop this 3D driver.
- 
+
  Permission is hereby granted, free of charge, to any person obtaining
  a copy of this software and associated documentation files (the
  "Software"), to deal in the Software without restriction, including
@@ -10,11 +10,11 @@
  distribute, sublicense, and/or sell copies of the Software, and to
  permit persons to whom the Software is furnished to do so, subject to
  the following conditions:
- 
+
  The above copyright notice and this permission notice (including the
  next paragraph) shall be included in all copies or substantial
  portions of the Software.
- 
+
  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
@@ -22,38 +22,26 @@
  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- 
+
  **********************************************************************/
  /*
   * Authors:
-  *   Keith Whitwell <keith@tungstengraphics.com>
+  *   Keith Whitwell <keithw@vmware.com>
   */
-     
+
 #include "brw_state.h"
 #include "intel_batchbuffer.h"
 #include "main/imports.h"
-#include "../glsl/ralloc.h"
+#include "util/hash_table.h"
+#include "util/ralloc.h"
 
-static void
-brw_track_state_batch(struct brw_context *brw,
-                     enum state_struct_type type,
-                     uint32_t offset,
-                     int size)
+uint32_t
+brw_state_batch_size(struct brw_context *brw, uint32_t offset)
 {
-   struct intel_batchbuffer *batch = &brw->intel.batch;
-
-   if (!brw->state_batch_list) {
-      /* Our structs are always aligned to at least 32 bytes, so
-       * our array doesn't need to be any larger
-       */
-      brw->state_batch_list = ralloc_size(brw, sizeof(*brw->state_batch_list) *
-                                         batch->bo->size / 32);
-   }
-
-   brw->state_batch_list[brw->state_batch_count].offset = offset;
-   brw->state_batch_list[brw->state_batch_count].size = size;
-   brw->state_batch_list[brw->state_batch_count].type = type;
-   brw->state_batch_count++;
+   struct hash_entry *entry =
+      _mesa_hash_table_search(brw->batch.state_batch_sizes,
+                              (void *) (uintptr_t) offset);
+   return entry ? (uintptr_t) entry->data : 0;
 }
 
 /**
@@ -64,7 +52,7 @@ brw_track_state_batch(struct brw_context *brw,
  * margin (4096 bytes, even if the object is just a 20-byte surface
  * state), and more buffers to walk and count for aperture size checking.
  *
- * However, due to the restrictions inposed by the aperture size
+ * However, due to the restrictions imposed by the aperture size
  * checking performance hacks, we can't have the batch point at a
  * separate indirect state buffer, because once the batch points at
  * it, no more relocations can be added to it.  So, we sneak these
@@ -72,12 +60,11 @@ brw_track_state_batch(struct brw_context *brw,
  */
 void *
 brw_state_batch(struct brw_context *brw,
-               enum state_struct_type type,
-               int size,
-               int alignment,
-               uint32_t *out_offset)
+                int size,
+                int alignment,
+                uint32_t *out_offset)
 {
-   struct intel_batchbuffer *batch = &brw->intel.batch;
+   struct intel_batchbuffer *batch = &brw->batch;
    uint32_t offset;
 
    assert(size < batch->bo->size);
@@ -88,15 +75,18 @@ brw_state_batch(struct brw_context *brw,
     * space, then flush and try again.
     */
    if (batch->state_batch_offset < size ||
-       offset < 4*batch->used + batch->reserved_space) {
-      intel_batchbuffer_flush(&brw->intel);
+       offset < 4 * USED_BATCH(*batch) + batch->reserved_space) {
+      intel_batchbuffer_flush(brw);
       offset = ROUND_DOWN_TO(batch->state_batch_offset - size, alignment);
    }
 
    batch->state_batch_offset = offset;
 
-   if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
-      brw_track_state_batch(brw, type, offset, size);
+   if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
+      _mesa_hash_table_insert(batch->state_batch_sizes,
+                              (void *) (uintptr_t) offset,
+                              (void *) (uintptr_t) size);
+   }
 
    *out_offset = offset;
    return batch->map + (offset>>2);