intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_batch.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 81d034ce822770c8209347db2d0db0e52d2afad4..c71d2f301d25baf8fdbe80b9437ea96be1a6f704 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -40,7 +40,7 @@ brw_track_state_batch(struct brw_context *brw,
                      uint32_t offset,
                      int size)
 {
-   struct intel_batchbuffer *batch = &brw->intel.batch;
+   struct intel_batchbuffer *batch = &brw->batch;
 
    if (!brw->state_batch_list) {
       /* Our structs are always aligned to at least 32 bytes, so
@@ -56,6 +56,50 @@ brw_track_state_batch(struct brw_context *brw,
    brw->state_batch_count++;
 }
 
+/**
+ * Convenience function to populate a single drm_intel_aub_annotation data
+ * structure.
+ */
+static inline void
+make_annotation(drm_intel_aub_annotation *annotation, uint32_t type,
+                uint32_t subtype, uint32_t ending_offset)
+{
+   annotation->type = type;
+   annotation->subtype = subtype;
+   annotation->ending_offset = ending_offset;
+}
+
+/**
+ * Generate a set of aub file annotations for the current batch buffer, and
+ * deliver them to DRM.
+ *
+ * The "used" section of the batch buffer (the portion containing batch
+ * commands) is annotated with AUB_TRACE_TYPE_BATCH.  The remainder of the
+ * batch buffer (which contains data structures pointed to by batch commands)
+ * is annotated according to the type of each data structure.
+ */
+void
+brw_annotate_aub(struct brw_context *brw)
+{
+   unsigned annotation_count = 2 * brw->state_batch_count + 1;
+   drm_intel_aub_annotation annotations[annotation_count];
+   int a = 0;
+   make_annotation(&annotations[a++], AUB_TRACE_TYPE_BATCH, 0,
+                   4*brw->batch.used);
+   for (int i = brw->state_batch_count; i-- > 0; ) {
+      uint32_t type = brw->state_batch_list[i].type;
+      uint32_t start_offset = brw->state_batch_list[i].offset;
+      uint32_t end_offset = start_offset + brw->state_batch_list[i].size;
+      make_annotation(&annotations[a++], AUB_TRACE_TYPE_NOTYPE, 0,
+                      start_offset);
+      make_annotation(&annotations[a++], AUB_TRACE_TYPE(type),
+                      AUB_TRACE_SUBTYPE(type), end_offset);
+   }
+   assert(a == annotation_count);
+   drm_intel_bufmgr_gem_set_aub_annotations(brw->batch.bo, annotations,
+                                            annotation_count);
+}
+
 /**
  * Allocates a block of space in the batchbuffer for indirect state.
  *
@@ -77,7 +121,7 @@ brw_state_batch(struct brw_context *brw,
                int alignment,
                uint32_t *out_offset)
 {
-   struct intel_batchbuffer *batch = &brw->intel.batch;
+   struct intel_batchbuffer *batch = &brw->batch;
    uint32_t offset;
 
    assert(size < batch->bo->size);
@@ -89,13 +133,13 @@ brw_state_batch(struct brw_context *brw,
     */
    if (batch->state_batch_offset < size ||
        offset < 4*batch->used + batch->reserved_space) {
-      intel_batchbuffer_flush(&brw->intel);
+      intel_batchbuffer_flush(brw);
       offset = ROUND_DOWN_TO(batch->state_batch_offset - size, alignment);
    }
 
    batch->state_batch_offset = offset;
 
-   if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
+   if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_AUB)))
       brw_track_state_batch(brw, type, offset, size);
 
    *out_offset = offset;