#include "brw_state.h"
#include "brw_vs.h"
#include "brw_wm.h"
-#include "brw_vs.h"
-#include "brw_vec4_gs.h"
+#include "brw_gs.h"
+#include "brw_cs.h"
#define FILE_DEBUG_FLAG DEBUG_STATE
GLuint size, i;
size = cache->size * 3;
- items = calloc(1, size * sizeof(*items));
+ items = calloc(size, sizeof(*items));
for (i = 0; i < cache->size; i++)
for (c = cache->items[i]; c; c = next) {
*(void **)out_aux = ((char *)item->key + item->key_size);
if (item->offset != *inout_offset) {
- SET_DIRTY_BIT(cache, 1 << cache_id);
+ brw->ctx.NewDriverState |= (1 << cache_id);
*inout_offset = item->offset;
}
drm_intel_bo *new_bo;
new_bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
+ if (brw->has_llc)
+ drm_intel_gem_bo_map_unsynchronized(new_bo);
/* Copy any existing data that needs to be saved. */
if (cache->next_offset != 0) {
- drm_intel_bo_map(cache->bo, false);
- drm_intel_bo_subdata(new_bo, 0, cache->next_offset, cache->bo->virtual);
- drm_intel_bo_unmap(cache->bo);
+ if (brw->has_llc) {
+ memcpy(new_bo->virtual, cache->bo->virtual, cache->next_offset);
+ } else {
+ drm_intel_bo_map(cache->bo, false);
+ drm_intel_bo_subdata(new_bo, 0, cache->next_offset,
+ cache->bo->virtual);
+ drm_intel_bo_unmap(cache->bo);
+ }
}
+ if (brw->has_llc)
+ drm_intel_bo_unmap(cache->bo);
drm_intel_bo_unreference(cache->bo);
cache->bo = new_bo;
cache->bo_used_by_gpu = false;
/* Since we have a new BO in place, we need to signal the units
* that depend on it (state base address on gen5+, or unit state before).
*/
- SET_DIRTY_BIT(brw, BRW_NEW_PROGRAM_CACHE);
+ brw->ctx.NewDriverState |= BRW_NEW_PROGRAM_CACHE;
}
/**
const void *data,
const void *aux)
{
+ struct brw_context *brw = cache->brw;
int i;
struct brw_cache_item *item;
continue;
}
- drm_intel_bo_map(cache->bo, false);
+ if (!brw->has_llc)
+ drm_intel_bo_map(cache->bo, false);
ret = memcmp(cache->bo->virtual + item->offset, data, item->size);
- drm_intel_bo_unmap(cache->bo);
+ if (!brw->has_llc)
+ drm_intel_bo_unmap(cache->bo);
if (ret)
continue;
struct brw_cache_item *item,
const void *data)
{
+ struct brw_context *brw = cache->brw;
+
/* Allocate space in the cache BO for our new program. */
if (cache->next_offset + item->size > cache->bo->size) {
uint32_t new_size = cache->bo->size * 2;
/* If we would block on writing to an in-use program BO, just
* recreate it.
*/
- if (cache->bo_used_by_gpu) {
+ if (!brw->has_llc && cache->bo_used_by_gpu) {
+ perf_debug("Copying busy program cache buffer.\n");
brw_cache_new_bo(cache, cache->bo->size);
}
item->key = tmp;
- if (cache->n_items > cache->size * 1.5)
+ if (cache->n_items > cache->size * 1.5f)
rehash(cache);
hash %= cache->size;
cache->n_items++;
/* Copy data to the buffer */
- drm_intel_bo_subdata(cache->bo, item->offset, data_size, data);
+ if (brw->has_llc) {
+ memcpy((char *) cache->bo->virtual + item->offset, data, data_size);
+ } else {
+ drm_intel_bo_subdata(cache->bo, item->offset, data_size, data);
+ }
*out_offset = item->offset;
*(void **)out_aux = (void *)((char *)item->key + item->key_size);
- SET_DIRTY_BIT(cache, 1 << cache_id);
+ cache->brw->ctx.NewDriverState |= 1 << cache_id;
}
void
cache->size = 7;
cache->n_items = 0;
cache->items =
- calloc(1, cache->size * sizeof(struct brw_cache_item *));
+ calloc(cache->size, sizeof(struct brw_cache_item *));
cache->bo = drm_intel_bo_alloc(brw->bufmgr,
"program cache",
4096, 64);
-
- cache->aux_compare[BRW_VS_PROG] = brw_vs_prog_data_compare;
- cache->aux_compare[BRW_GS_PROG] = brw_gs_prog_data_compare;
- cache->aux_compare[BRW_WM_PROG] = brw_wm_prog_data_compare;
- cache->aux_free[BRW_VS_PROG] = brw_stage_prog_data_free;
- cache->aux_free[BRW_GS_PROG] = brw_stage_prog_data_free;
- cache->aux_free[BRW_WM_PROG] = brw_stage_prog_data_free;
+ if (brw->has_llc)
+ drm_intel_gem_bo_map_unsynchronized(cache->bo);
+
+ cache->aux_compare[BRW_CACHE_VS_PROG] = brw_vs_prog_data_compare;
+ cache->aux_compare[BRW_CACHE_GS_PROG] = brw_gs_prog_data_compare;
+ cache->aux_compare[BRW_CACHE_FS_PROG] = brw_wm_prog_data_compare;
+ cache->aux_compare[BRW_CACHE_CS_PROG] = brw_cs_prog_data_compare;
+ cache->aux_free[BRW_CACHE_VS_PROG] = brw_stage_prog_data_free;
+ cache->aux_free[BRW_CACHE_GS_PROG] = brw_stage_prog_data_free;
+ cache->aux_free[BRW_CACHE_FS_PROG] = brw_stage_prog_data_free;
+ cache->aux_free[BRW_CACHE_CS_PROG] = brw_stage_prog_data_free;
}
static void
struct brw_cache_item *c, *next;
GLuint i;
- DBG("%s\n", __FUNCTION__);
+ DBG("%s\n", __func__);
for (i = 0; i < cache->size; i++) {
for (c = cache->items[i]; c; c = next) {
/* We need to make sure that the programs get regenerated, since
* any offsets leftover in brw_context will no longer be valid.
*/
- SET_DIRTY_ALL(mesa);
- SET_DIRTY_ALL(brw);
- SET_DIRTY_ALL(cache);
+ brw->NewGLState |= ~0;
+ brw->ctx.NewDriverState |= ~0ull;
intel_batchbuffer_flush(brw);
}
brw_destroy_cache(struct brw_context *brw, struct brw_cache *cache)
{
- DBG("%s\n", __FUNCTION__);
+ DBG("%s\n", __func__);
+ if (brw->has_llc)
+ drm_intel_bo_unmap(cache->bo);
drm_intel_bo_unreference(cache->bo);
cache->bo = NULL;
brw_clear_cache(brw, cache);