intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_cache.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index e26f33ad0820e6920b3ccf9b78f3c0177e58fda5..ddb275fa218e6d484a476aa24d2ad30019f820e4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -168,10 +168,9 @@ static void
 brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
 {
    struct brw_context *brw = cache->brw;
-   struct intel_context *intel = &brw->intel;
    drm_intel_bo *new_bo;
 
-   new_bo = drm_intel_bo_alloc(intel->bufmgr, "program cache", new_size, 64);
+   new_bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
 
    /* Copy any existing data that needs to be saved. */
    if (cache->next_offset != 0) {
@@ -328,7 +327,6 @@ brw_upload_cache(struct brw_cache *cache,
 void
 brw_init_caches(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
    struct brw_cache *cache = &brw->cache;
 
    cache->brw = brw;
@@ -338,7 +336,7 @@ brw_init_caches(struct brw_context *brw)
    cache->items =
       calloc(1, cache->size * sizeof(struct brw_cache_item *));
 
-   cache->bo = drm_intel_bo_alloc(intel->bufmgr,
+   cache->bo = drm_intel_bo_alloc(brw->bufmgr,
                                  "program cache",
                                  4096, 64);
 
@@ -388,8 +386,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
 void
 brw_state_cache_check_size(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-
    /* un-tuned guess.  Each object is generally a page, so 2000 of them is 8 MB of
     * state cache.
     */