i965: Create a macro for setting a dirty bit.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_cache.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index b0986ea08fd4c3e347535ff843f148cb222b2745..df2d806e7f6fc04ef71e59c5cb14c6971c675027 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -158,7 +158,7 @@ brw_search_cache(struct brw_cache *cache,
    *(void **)out_aux = ((char *)item->key + item->key_size);
 
    if (item->offset != *inout_offset) {
-      brw->state.dirty.cache |= (1 << cache_id);
+      SET_DIRTY_BIT(cache, 1 << cache_id);
       *inout_offset = item->offset;
    }
 
@@ -187,7 +187,7 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
    /* Since we have a new BO in place, we need to signal the units
     * that depend on it (state base address on gen5+, or unit state before).
     */
-   brw->state.dirty.brw |= BRW_NEW_PROGRAM_CACHE;
+   SET_DIRTY_BIT(brw, BRW_NEW_PROGRAM_CACHE);
 }
 
 /**
@@ -276,6 +276,7 @@ brw_upload_cache(struct brw_cache *cache,
                 uint32_t *out_offset,
                 void *out_aux)
 {
+   struct brw_context *brw = cache->brw;
    struct brw_cache_item *item = CALLOC_STRUCT(brw_cache_item);
    GLuint hash;
    void *tmp;
@@ -320,7 +321,7 @@ brw_upload_cache(struct brw_cache *cache,
 
    *out_offset = item->offset;
    *(void **)out_aux = (void *)((char *)item->key + item->key_size);
-   cache->brw->state.dirty.cache |= 1 << cache_id;
+   SET_DIRTY_BIT(cache, 1 << cache_id);
 }
 
 void