i965: Add HiZ operation state to brw_context

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_dump.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c
index cc2c36c7e99b32810a6da4832ce7eeffdf2c527a..cb7a3ef73d3bca74c9c1c7ed6e37518ea6f9cd57 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -141,7 +141,7 @@ static void dump_sf_state(struct brw_context *brw, uint32_t offset)
    batch_out(brw, name, offset, 3, "thread3\n");
    batch_out(brw, name, offset, 4, "thread4: %d threads\n",
             sf->thread4.max_threads + 1);
-   batch_out(brw, name, offset, 5, "sf5\n");
+   batch_out(brw, name, offset, 5, "sf5: viewport offset\n");
    batch_out(brw, name, offset, 6, "sf6\n");
    batch_out(brw, name, offset, 7, "sf7\n");
 }
@@ -384,7 +384,21 @@ static void dump_depth_stencil_state(struct brw_context *brw, uint32_t offset)
             ds->ds2.depth_write_enable ? "en" : "dis");
 }
 
-static void dump_cc_state(struct brw_context *brw, uint32_t offset)
+static void dump_cc_state_gen4(struct brw_context *brw, uint32_t offset)
+{
+   const char *name = "CC";
+
+   batch_out(brw, name, offset, 0, "cc0\n");
+   batch_out(brw, name, offset, 1, "cc1\n");
+   batch_out(brw, name, offset, 2, "cc2\n");
+   batch_out(brw, name, offset, 3, "cc3\n");
+   batch_out(brw, name, offset, 4, "cc4: viewport offset\n");
+   batch_out(brw, name, offset, 5, "cc5\n");
+   batch_out(brw, name, offset, 6, "cc6\n");
+   batch_out(brw, name, offset, 7, "cc7\n");
+}
+
+static void dump_cc_state_gen6(struct brw_context *brw, uint32_t offset)
 {
    const char *name = "CC";
    struct gen6_color_calc_state *cc = brw->intel.batch.bo->virtual + offset;
@@ -441,6 +455,23 @@ dump_vs_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
    }
 }
 
+static void
+dump_wm_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
+{
+   const char *name = "WM_CONST";
+   struct intel_context *intel = &brw->intel;
+   uint32_t *as_uint = intel->batch.bo->virtual + offset;
+   float *as_float = intel->batch.bo->virtual + offset;
+   int i;
+
+   for (i = 0; i < size / 4; i += 4) {
+      batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
+               i / 4,
+               as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
+               as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
+   }
+}
+
 static void dump_binding_table(struct brw_context *brw, uint32_t offset,
                               uint32_t size)
 {
@@ -554,7 +585,10 @@ dump_state_batch(struct brw_context *brw)
         dump_depth_stencil_state(brw, offset);
         break;
       case AUB_TRACE_CC_STATE:
-        dump_cc_state(brw, offset);
+        if (intel->gen >= 6)
+           dump_cc_state_gen6(brw, offset);
+        else
+           dump_cc_state_gen4(brw, offset);
         break;
       case AUB_TRACE_BLEND_STATE:
         dump_blend_state(brw, offset);
@@ -585,6 +619,9 @@ dump_state_batch(struct brw_context *brw)
       case AUB_TRACE_VS_CONSTANTS:
         dump_vs_constants(brw, offset, size);
         break;
+      case AUB_TRACE_WM_CONSTANTS:
+        dump_wm_constants(brw, offset, size);
+        break;
       default:
         break;
       }