i965: perf: cleanup detection of kernel support for loadable configs

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_upload.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9e64213c2e7b49b57e003a58cbc1b0acd9fdb542..20c59c6e9dc4c592e2dae73dcdc03fead795ec18 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -66,28 +66,36 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
       brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
                               REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
                               GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
+      /* From gen10 workaround table in h/w specs:
+       *
+       *    "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
+       *     a value of 0xFFFF"
+       *
+       * This means that we end up setting the entire 3D_MODE state. Bits
+       * in this register control things such as slice hashing and we want
+       * the default values of zero at the moment.
+       */
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
+      OUT_BATCH(0xFFFF << 16);
+      ADVANCE_BATCH();
    }
 
    if (devinfo->gen == 9) {
       /* Recommended optimizations for Victim Cache eviction and floating
        * point blending.
        */
-      BEGIN_BATCH(3);
-      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-      OUT_BATCH(GEN7_CACHE_MODE_1);
-      OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
-                REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
-                GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
-                GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
-      ADVANCE_BATCH();
+      brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
+                              REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
+                              REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
+                              GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
+                              GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
 
       if (gen_device_info_is_9lp(devinfo)) {
-         BEGIN_BATCH(3);
-         OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-         OUT_BATCH(GEN7_GT_MODE);
-         OUT_BATCH(GEN9_SUBSLICE_HASHING_MASK_BITS |
-                   GEN9_SUBSLICE_HASHING_16x16);
-         ADVANCE_BATCH();
+         brw_load_register_imm32(brw, GEN7_GT_MODE,
+                                 GEN9_SUBSLICE_HASHING_MASK_BITS |
+                                 GEN9_SUBSLICE_HASHING_16x16);
       }
    }
 
@@ -196,7 +204,7 @@ void brw_init_state( struct brw_context *brw )
    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
    ctx->DriverFlags.NewShaderStorageBuffer = BRW_NEW_UNIFORM_BUFFER;
    ctx->DriverFlags.NewTextureBuffer = BRW_NEW_TEXTURE_BUFFER;
-   ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
+   ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_UNIFORM_BUFFER;
    ctx->DriverFlags.NewImageUnits = BRW_NEW_IMAGE_UNITS;
    ctx->DriverFlags.NewDefaultTessLevels = BRW_NEW_DEFAULT_TESS_LEVELS;
    ctx->DriverFlags.NewIntelConservativeRasterization = BRW_NEW_CONSERVATIVE_RASTERIZATION;
@@ -315,7 +323,6 @@ static struct dirty_bit_map brw_bits[] = {
    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
    DEFINE_BIT(BRW_NEW_STATS_WM),
    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
-   DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),
    DEFINE_BIT(BRW_NEW_IMAGE_UNITS),
    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),