intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_upload.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 39fe6d265640db075c2ca2a28d0785cab6c5e619..64e0bcf8e8f2cb97da516f67c484ec482a7db0db 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -41,6 +41,9 @@ static const struct brw_tracked_state *gen4_atoms[] =
 {
    &brw_vs_prog, /* must do before GS prog, state base address. */
    &brw_gs_prog, /* must do before state base address */
+
+   &brw_interpolation_map,
+
    &brw_clip_prog, /* must do before state base address */
    &brw_sf_prog, /* must do before state base address */
    &brw_wm_prog, /* must do before state base address */
@@ -65,7 +68,8 @@ static const struct brw_tracked_state *gen4_atoms[] =
    &brw_vs_binding_table,
    &brw_wm_binding_table,
 
-   &brw_samplers,
+   &brw_fs_samplers,
+   &brw_vs_samplers,
 
    /* These set up state for brw_psp_urb_cbs */
    &brw_wm_unit,
@@ -140,7 +144,8 @@ static const struct brw_tracked_state *gen6_atoms[] =
    &gen6_gs_binding_table,
    &brw_wm_binding_table,
 
-   &brw_samplers,
+   &brw_fs_samplers,
+   &brw_vs_samplers,
    &gen6_sampler_state,
    &gen6_multisample_state,
 
@@ -203,7 +208,8 @@ static const struct brw_tracked_state *gen7_atoms[] =
    &brw_vs_binding_table,
    &brw_wm_binding_table,
 
-   &gen7_samplers,
+   &brw_fs_samplers,
+   &brw_vs_samplers,
    &gen6_multisample_state,
 
    &gen7_disable_stages,
@@ -237,8 +243,6 @@ static const struct brw_tracked_state *gen7_atoms[] =
 static void
 brw_upload_initial_gpu_state(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-
    /* On platforms with hardware contexts, we can set our initial GPU state
     * right away rather than doing it via state atoms.  This saves a small
     * amount of overhead on every draw call.
@@ -248,7 +252,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
 
    brw_upload_invariant_state(brw);
 
-   if (intel->gen >= 7) {
+   if (brw->gen >= 7) {
       gen7_allocate_push_constants(brw);
    }
 }
@@ -260,10 +264,10 @@ void brw_init_state( struct brw_context *brw )
 
    brw_init_caches(brw);
 
-   if (brw->intel.gen >= 7) {
+   if (brw->gen >= 7) {
       atoms = gen7_atoms;
       num_atoms = ARRAY_SIZE(gen7_atoms);
-   } else if (brw->intel.gen == 6) {
+   } else if (brw->gen == 6) {
       atoms = gen6_atoms;
       num_atoms = ARRAY_SIZE(gen6_atoms);
    } else {
@@ -386,6 +390,7 @@ static struct dirty_bit_map brw_bits[] = {
    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
+   DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
    {0, 0, 0}
 };
 
@@ -442,8 +447,7 @@ brw_print_dirty_count(struct dirty_bit_map *bit_map)
  */
 void brw_upload_state(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
-   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &brw->ctx;
    struct brw_state_flags *state = &brw->state.dirty;
    int i;
    static int dirty_count = 0;
@@ -465,6 +469,11 @@ void brw_upload_state(struct brw_context *brw)
       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
    }
 
+   if (brw->geometry_program != ctx->GeometryProgram._Current) {
+      brw->geometry_program = ctx->GeometryProgram._Current;
+      brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
+   }
+
    if (brw->vertex_program != ctx->VertexProgram._Current) {
       brw->vertex_program = ctx->VertexProgram._Current;
       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;