i965/gen9: Optimize slice and subslice load balancing behavior.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_upload.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index cc21aca494542dec408bdbc7dad2e708a879cf03..7a2daf4a5335c23e7152788dcabe78f8915a1d6c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -48,7 +48,7 @@
 void
 brw_enable_obj_preemption(struct brw_context *brw, bool enable)
 {
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
+   ASSERTED const struct gen_device_info *devinfo = &brw->screen->devinfo;
    assert(devinfo->gen >= 9);
 
    if (enable == brw->object_preemption)
@@ -109,27 +109,19 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
       brw_load_register_imm32(brw, GEN8_L3CNTLREG,
                               GEN8_L3CNTLREG_EDBC_NO_HANG);
 
-      /* WA_2204188704: Pixel Shader Panic dispatch must be disabled.
-       */
-       brw_load_register_imm32(brw, COMMON_SLICE_CHICKEN3,
-                               PS_THREAD_PANIC_DISPATCH_MASK |
-                               PS_THREAD_PANIC_DISPATCH);
+       /* WaEnableStateCacheRedirectToCS:icl */
+       brw_load_register_imm32(brw, SLICE_COMMON_ECO_CHICKEN1,
+                               GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE |
+                               REG_MASK(GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE));
    }
 
-   if (devinfo->gen == 10 || devinfo->gen == 11) {
-      /* From gen10 workaround table in h/w specs:
-       *
-       *    "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
-       *     a value of 0xFFFF"
-       *
-       * This means that we end up setting the entire 3D_MODE state. Bits
-       * in this register control things such as slice hashing and we want
-       * the default values of zero at the moment.
-       */
-      BEGIN_BATCH(2);
-      OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
-      OUT_BATCH(0xFFFF << 16);
-      ADVANCE_BATCH();
+   /* hardware specification recommends disabling repacking for
+    * the compatibility with decompression mechanism in display controller.
+    */
+   if (devinfo->disable_ccs_repack) {
+      brw_load_register_imm32(brw, GEN7_CACHE_MODE_0,
+                              GEN11_DISABLE_REPACKING_FOR_COMPRESSION |
+                              REG_MASK(GEN11_DISABLE_REPACKING_FOR_COMPRESSION));
    }
 
    if (devinfo->gen == 9) {
@@ -141,12 +133,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
                               REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
                               GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
                               GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
-
-      if (gen_device_info_is_9lp(devinfo)) {
-         brw_load_register_imm32(brw, GEN7_GT_MODE,
-                                 GEN9_SUBSLICE_HASHING_MASK_BITS |
-                                 GEN9_SUBSLICE_HASHING_16x16);
-      }
    }
 
    if (devinfo->gen >= 8) {
@@ -350,7 +336,6 @@ static struct dirty_bit_map mesa_bits[] = {
    DEFINE_BIT(_NEW_TRANSFORM),
    DEFINE_BIT(_NEW_VIEWPORT),
    DEFINE_BIT(_NEW_TEXTURE_STATE),
-   DEFINE_BIT(_NEW_ARRAY),
    DEFINE_BIT(_NEW_RENDERMODE),
    DEFINE_BIT(_NEW_BUFFERS),
    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
@@ -552,6 +537,9 @@ brw_upload_pipeline_state(struct brw_context *brw,
 
    brw_select_pipeline(brw, pipeline);
 
+   if (pipeline == BRW_RENDER_PIPELINE && brw->current_hash_scale != 1)
+      brw_emit_hashing_mode(brw, UINT_MAX, UINT_MAX, 1);
+
    if (unlikely(INTEL_DEBUG & DEBUG_REEMIT)) {
       /* Always re-emit all state. */
       brw->NewGLState = ~0;