Revert "i965/icl: Add WA_2204188704 to disable pixel shader panic dispatch"

[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_upload.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 5743fd5b8aefa1c0e3c49410fd4cf5fc17c0db2f..c41d9551a1e22c48c12d147ab64b7954cb8e800d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -109,12 +109,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
       brw_load_register_imm32(brw, GEN8_L3CNTLREG,
                               GEN8_L3CNTLREG_EDBC_NO_HANG);
 
-      /* WA_2204188704: Pixel Shader Panic dispatch must be disabled.
-       */
-       brw_load_register_imm32(brw, COMMON_SLICE_CHICKEN3,
-                               PS_THREAD_PANIC_DISPATCH_MASK |
-                               PS_THREAD_PANIC_DISPATCH);
-
        /* WaEnableStateCacheRedirectToCS:icl */
        brw_load_register_imm32(brw, SLICE_COMMON_ECO_CHICKEN1,
                                GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE |
@@ -355,7 +349,6 @@ static struct dirty_bit_map mesa_bits[] = {
    DEFINE_BIT(_NEW_TRANSFORM),
    DEFINE_BIT(_NEW_VIEWPORT),
    DEFINE_BIT(_NEW_TEXTURE_STATE),
-   DEFINE_BIT(_NEW_ARRAY),
    DEFINE_BIT(_NEW_RENDERMODE),
    DEFINE_BIT(_NEW_BUFFERS),
    DEFINE_BIT(_NEW_CURRENT_ATTRIB),